[参考译文] TMS320F28386D：外部中断只能触发 CPU1

void DMACH1Config(volatile Uint16 *DMA_Source, volatile Uint16 *DMA_Dest, Uint16 wordLen, Uint16 TriggerSource)
{
    Uint16 tsize = wordLen % 32 ? (wordLen/32 + 1) : wordLen/32;
	Uint16 bsize = wordLen / tsize;

	EALLOW;

	// Disable DMA channel
	DmaRegs.CH1.CONTROL.bit.RUN = 0;

	// Configure DMA Channel 1 (32-bit datasize)
	// Set up SOURCE address:
	DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;	// Point to beginning of source buffer
	DmaRegs.CH1.SRC_ADDR_SHADOW		= (Uint32)DMA_Source;

	// Set up DESTINATION address:
	DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;		// Point to beginning of destination buffer
	DmaRegs.CH1.DST_ADDR_SHADOW		= (Uint32)DMA_Dest;

	// Set up BURST registers:
	DmaRegs.CH1.BURST_SIZE.all = bsize-1;				// Number of words (X-1) transferred in a burst
	DmaRegs.CH1.SRC_BURST_STEP = 2;						// Increment source addr between each word transferred
	DmaRegs.CH1.DST_BURST_STEP = 2;						// Increment dest addr between each word transferred

	// Set up TRANSFER registers:
	DmaRegs.CH1.TRANSFER_SIZE = tsize-1;				// Number of bursts (X-1) per transfer, DMA interrupt will occur after completed transfer
	DmaRegs.CH1.SRC_TRANSFER_STEP = 2;					// TRANSFER_STEP is ignored when WRAP occurs
	DmaRegs.CH1.DST_TRANSFER_STEP = 2;					// TRANSFER_STEP is ignored when WRAP occurs

	// Set up WRAP registers:
	DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF;					// Wrap source address after N bursts
	DmaRegs.CH1.SRC_WRAP_STEP = 0;						// Step for source wrap

	DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF;					// Wrap destination address after N bursts
	DmaRegs.CH1.DST_WRAP_STEP = 0;						// Step for destination wrap

	DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = TriggerSource;

	// Set up MODE Register:
	DmaRegs.CH1.MODE.bit.PERINTSEL	= 1;				// Should be hard coded to channel, above now selects source, 36:EPWM1.SOCA
	DmaRegs.CH1.MODE.bit.PERINTE	= PERINT_ENABLE;	// Peripheral interrupt enable
	DmaRegs.CH1.MODE.bit.ONESHOT	= ONESHOT_ENABLE;	// Oneshot enable
	DmaRegs.CH1.MODE.bit.CONTINUOUS	= CONT_ENABLE;		// Continous enable
	DmaRegs.CH1.MODE.bit.OVRINTE	= OVRFLOW_DISABLE;	// Enable/disable the overflow interrupt
	DmaRegs.CH1.MODE.bit.DATASIZE	= THIRTYTWO_BIT;	// 16-bit/32-bit data size transfers
	DmaRegs.CH1.MODE.bit.CHINTMODE	= CHINT_END;		// Generate interrupt to CPU at beginning/end of transfer
	DmaRegs.CH1.MODE.bit.CHINTE		= CHINT_ENABLE;

	// Clear any spurious flags:
	DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;				// Clear any spurious interrupt flags
	DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;					// Clear any spurious sync error flags

	// Initialize PIE vector for CPU interrupt:
	PieCtrlRegs.PIEIER7.bit.INTx1 = 1;

	// This function starts DMA Channel 1.
	DmaRegs.CH1.CONTROL.bit.RUN = 1;

	EDIS;