[参考译文] TMS320F2808：从闪存运行应用程序

Mac 您好、  

将应用程序放置到闪存中并不取决于 hex2000实用程序命令、而是取决于您如何将应用程序映射到链接器命令文件中的存储器。 存储器的所有初始化部分、尤其是 CODE_START、是否都映射到闪存？ 您还可以尝试通过在链接器命令文件中使用 align (8)指令将闪存的所有部分对齐到128位边界-这将确保闪存 API 传递128位对齐地址。  

我还看到您在使用 hex2000实用程序命令中的二进制标志而不是 ASCII 标志、这是故意的吗？

谢谢、  

Anu

尊敬的 Anu：
CODE_START 映射到地址0x3F7FF6。  我没有创建我正在使用的测试应用、因此我不熟悉它链接方式的细节、但是我能够使用 JTAG 对闪存进行编程、然后在 CPU 重新启动时运行应用。  我已经创建了自己的测试应用、但没有尝试使用 JTAG 上传。  我遵循 SPRA958L (从 TMS320F28xxx DSP 上的内部闪存运行一个应用)作为连接我的应用的指南。 我将尝试链接 ALIGN (8)指令并返回报告。  我正在使用二进制标志来模仿 CCS 中的默认选项对于我所模仿的十六进制实用程序而言的样子。

您的、

MAC  

我很幸运地尝试使用 align (8)指令进行链接。  我还尝试使用 ASCII 选项而不是二进制。  为了发送 ASCII 数据、我需要将其转换为串行程序中的二进制数据、然后再无论如何发送。  任何其他建议都很有用、

您的、

MAC

Anu、

我的基本格式是循环浏览应用程序文件两次。  对每个块进行编程并验证每个块、然后第二次验证应用。

Status = Flash_Program(block_address + (0x100 * l), Buffer, 0x100, &FlashStatus);
                if(Status != STATUS_SUCCESS)
                {
                    Example_Error(Status);
                    return;
                }

在我对每个数据块进行编程和验证之后、我无需执行程序步骤即可验证整个应用程序(即再次通过串行发送文件以检查所有数据是否在预期位置)。

我尚未通过 JTAG 查看特定的存储器地址、以查看我预期的值是否还在那里、但我认为闪存 API 正在将我输入的值正确地放入闪存中。

您的、

MAC

Maurice、  

这听起来不错、只要仔细检查一下、我就会在您通过 JTAG 加载应用程序时检查存储器的内容、而不是使用引导加载程序加载应用程序时检查存储器的内容、以确保没有差异。  

对应用程序进行编程后重新启动 CPU 时、您的器件处于哪种引导模式？

谢谢、  

Anu

Anu、

GPI18、GPI29和 GPIO34都是高电平、因此它将引导至闪存

MAC

MAC、  

您能否共享您正在使用的链接器命令文件？

谢谢、  

Anu

Anu、

我稍微修改了 F2808头文件和外设示例代码中的 F2808.cmd 文件、以包括 SPRA958L 中提到的部分(上面提到)。  这是我添加 ALIGN (8)指令之前的文件。

/*
// TI File $Revision: /main/4 $
// Checkin $Date: August 2, 2006   16:57:00 $
//###########################################################################
//
// FILE:	F2808.cmd
//
// TITLE:	Linker Command File For F2808 Device
//
//###########################################################################
// $TI Release: DSP280x C/C++ Header Files V1.70 $
// $Release Date: July 27, 2009 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file, 
// add the header linker command file directly to the project. 
// The header linker command file is required to link the
// peripheral structures to the proper locations within 
// the memory map.
//
// The header linker files are found in <base>\DSP280x_Headers\cmd
//   
// For BIOS applications add:      DSP280x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP280x_Headers_nonBIOS.cmd    
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP280x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP280x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP280x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2808  
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes: 
         Memory blocks on F2808 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.  
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program 
         and/or data. 
         
         L0/L1 and H0 memory blocks are mirrored - that is
         they can be accessed in high memory or low memory.
         For simplicity only one instance is used in this
         linker file. 
         
         Contiguous SARAM memory blocks or flash sectors can be
         be combined if required to create a larger memory block. 
*/

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   
   ROM         : origin = 0x3FF000, length = 0x000FC0     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   RAMM0       : origin = 0x000000, length = 0x000400     /* on-chip RAM block M0 */
   BOOT_RSVD   : origin = 0x000400, length = 0x000080     /* Part of M1, BOOT rom will use this for stack */
   RAMM1       : origin = 0x000480, length = 0x000380     /* on-chip RAM block M1 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */
   RAMH0       : origin = 0x3FA000, length = 0x002000     /* on-chip RAM block H0 */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : > FLASHA      PAGE = 0
   .const			   : > FLASHA      PAGE = 0
   .pinit              : > FLASHA      PAGE = 0
   .text               : > FLASHA      PAGE = 0
   codestart           : > BEGIN       PAGE = 0
   .cio                : > RAML1       PAGE = 1
   .sysmem             : > RAML1       PAGE = 1
   .esysmem            : > RAML1       PAGE = 1
   .bss                : > RAML1       PAGE = 1

   ramfuncs            : LOAD = FLASHD, 
                         RUN = RAML0, 
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0

   csmpasswds          : > CSM_PWL     PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0
   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 1
   .ebss               : > RAML1       PAGE = 1
   .esysmem            : > RAMH0       PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA      PAGE = 0
   .switch             : > FLASHA      PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHC      PAGE = 0                  /* Math Code */
   IQmathTables        : > ROM         PAGE = 0, TYPE = NOLOAD   /* Math Tables In ROM */

   /* .reset is a standard section used by the compiler.  It contains the */ 
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */ 
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

您的、

MAC

这是包含 align (8)指令的文件

/*
// TI File $Revision: /main/4 $
// Checkin $Date: August 2, 2006   16:57:00 $
//###########################################################################
//
// FILE:	F2808.cmd
//
// TITLE:	Linker Command File For F2808 Device
//
//###########################################################################
// $TI Release: DSP280x C/C++ Header Files V1.70 $
// $Release Date: July 27, 2009 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file, 
// add the header linker command file directly to the project. 
// The header linker command file is required to link the
// peripheral structures to the proper locations within 
// the memory map.
//
// The header linker files are found in <base>\DSP280x_Headers\cmd
//   
// For BIOS applications add:      DSP280x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP280x_Headers_nonBIOS.cmd    
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP280x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP280x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP280x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2808  
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes: 
         Memory blocks on F2808 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.  
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program 
         and/or data. 
         
         L0/L1 and H0 memory blocks are mirrored - that is
         they can be accessed in high memory or low memory.
         For simplicity only one instance is used in this
         linker file. 
         
         Contiguous SARAM memory blocks or flash sectors can be
         be combined if required to create a larger memory block. 
*/

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   
   ROM         : origin = 0x3FF000, length = 0x000FC0     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   RAMM0       : origin = 0x000000, length = 0x000400     /* on-chip RAM block M0 */
   BOOT_RSVD   : origin = 0x000400, length = 0x000080     /* Part of M1, BOOT rom will use this for stack */
   RAMM1       : origin = 0x000480, length = 0x000380     /* on-chip RAM block M1 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */
   RAMH0       : origin = 0x3FA000, length = 0x002000     /* on-chip RAM block H0 */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : > FLASHA      PAGE = 0 ALIGN(8)
   .const			   : > FLASHA      PAGE = 0 ALIGN(8)
   .pinit              : > FLASHA      PAGE = 0 ALIGN(8)
   .text               : > FLASHA      PAGE = 0 ALIGN(8)
   codestart           : > BEGIN       PAGE = 0
   .cio                : > RAML1       PAGE = 1 ALIGN(8)
   .sysmem             : > RAML1       PAGE = 1 ALIGN(8)
   .esysmem            : > RAML1       PAGE = 1 ALIGN(8)
   .bss                : > RAML1       PAGE = 1 ALIGN(8)

   ramfuncs            : LOAD = FLASHD, 
                         RUN = RAML0, 
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0,
                         ALIGN(8)

   csmpasswds          : > CSM_PWL     PAGE = 0 ALIGN(8)
   csm_rsvd            : > CSM_RSVD    PAGE = 0 ALIGN(8)
   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 1 ALIGN(8)
   .ebss               : > RAML1       PAGE = 1 ALIGN(8)
   .esysmem            : > RAMH0       PAGE = 1 ALIGN(8)

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA      PAGE = 0 ALIGN(8)
   .switch             : > FLASHA      PAGE = 0 ALIGN(8)

   /* Allocate IQ math areas: */
   IQmath              : > FLASHC      PAGE = 0                  /* Math Code */
   IQmathTables        : > ROM         PAGE = 0, TYPE = NOLOAD   /* Math Tables In ROM */

   /* .reset is a standard section used by the compiler.  It contains the */ 
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */ 
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

MAC、  

我将对此进行回顾、并在明天返回给您。

谢谢、  

Anu

Anu、
正在检入。

MAC  

MAC、  

初始化段看起来像预期的那样位于闪存中。 在通过 JTAG 加载应用程序之后、您是否能够检查闪存中的内容？与通过引导加载程序加载的内容相比、您是否能够检查闪存中的内容？

您还可以继续执行并取出 align 指令、这是不需要的。  

谢谢、  

Anu

Anu、

我无法获得 JTAG。  当我找到一个 JTAG 时、我将尝试使用它进行检查(我知道我们有一些 JTAG、但它们连接在一起)、 但我确实认为、当我运行两个验证步骤并且这两个步骤都通过时、我期望的值会被编程(一个在我对块进行编程后、另一个在我完成文件编程后)。   与此同时、我还可以进行测试吗？  只需仔细检查、从闪存运行引导表应该起作用、对吧？

您的、

MAC

MAC、  

我认为检查闪存的内容将是最有帮助的。  

我回顾了该主题、注意到您说的串行程序仅发送二进制数据。 您发送二进制数据而不是 ASCII 数据是否有具体原因？ 是否可以尝试修改串行程序以将 ASCII 数据发送到引导加载程序？

谢谢、  

Anu