请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。
器件型号：TMS320F28069 您好！
我们一直在为交流/直流转换器应用-2级三相转换器开发 TMS320F28069 DSP。 对于该转换器、我们使用 SPWM +三次谐波调制技术来使用相移三角法。 开关频率为6.4kHz、我们在 ePWM 模块中使用一个递增和递减计数器。 PWM 载波(TPWM)的时间周期为156 μ s。 此外、对交流/直流转换器的控制已写入计时器0 ISR、该 ISR 已设置为125uec (ISR 时间)。
输入交流电压为182Vrms (线对线)、输出直流总线电压范围为325V 至420V
ePWM 模块的配置如下：
void InitEPwm1()
{
EALLOW;
EPwm1Regs.AQSFRC.bit.RLDCSF=3;
EPwm1Regs.TZSEL.bit.OSHT1 = 1;
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm1Regs.TBPRD = 7030; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm1Regs.CMPA.half.CMPA = 3500;
EPwm1Regs.CMPB = 3500;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;
// Active Low PWMs - Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
EPwm1Regs.DBRED = 270;
EPwm1Regs.DBFED = 270;
EDIS;
}
void InitEPwm2()
{
EALLOW;
EPwm2Regs.AQSFRC.bit.RLDCSF=3;
EPwm2Regs.TZSEL.bit.OSHT1 = 1;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm2Regs.TBPRD = pwm_time_prd; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS =(unsigned int)(((float)7030* 2)/3); // Phase is 0
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; //for shifted trangle
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm2Regs.CMPA.half.CMPA = 3500;
EPwm2Regs.CMPB = 3500;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;
EPwm2Regs.AQCTLB.bit.CBD = AQ_SET;
// Active Low complementary PWMs - setup the deadband
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
EPwm2Regs.DBRED = 270;
EPwm2Regs.DBFED = 270;
EDIS;
}
void InitEPwm3()
{
EALLOW;
EPwm3Regs.AQSFRC.bit.RLDCSF=3; //Lately Added For I/P Cap Short Circuit
EPwm3Regs.TZSEL.bit.OSHT1 = 1;
EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm3Regs.TBPRD = pwm_time_prd; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = (unsigned int)(((float)7030* 2)/3); // Phase is 0
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm3Regs.CMPA.half.CMPA = 3500;
EPwm3Regs.CMPB = 3500;
// Set actions
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm3Regs.AQCTLB.bit.CBU = AQ_SET;
EPwm3Regs.AQCTLB.bit.CBD = AQ_SET;
// Active high complementary PWMs - Setup the deadband
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC ;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
EPwm3Regs.DBRED = 270;
EPwm3Regs.DBFED = 270;
EDIS;
}
当我们将直流总线电压设置为351V 或更低时、转换器工作正常、但当直流总线电压设置为405V (超过400V)时、转换器由于 SAT 跳闸问题而无法工作。 由于同一桥臂的顶部和底部 IGBT 同时导通、因此会产生 SAT 跳闸问题。 请查看下图、其中显示两个脉冲同时导通。
尽管我们提供了3微秒的足够死区时间、并且 ePWM 模块配置为 AHC (高电平有效互补)模式、但如果我们尝试生成405V 的直流总线电压、我们将面临两个脉冲同时导通的问题
请您提出建议以解决上述问题。 如果您需要更多信息、请告诉我。
谢谢、
此致、
普拉什兰特
