[参考译文] TMS320F280025C：在 TMS320f280025C 上配置 CMPSS 时出现问题

#include <f28002x_device.h>
#include "driverlib.h"
#include "utils.h"
#include "device.h"
#include "board.h"
#include "config.h"

float init_EPWM();
void init_cmpss();

void main(void)
{
    // Initialize device clock and peripherals
    Device_init();
    // Disable pin locks and enable internal pullups.
    Device_initGPIO();
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    Interrupt_initModule();
    // Initialize the PIE vector table with pointers to the shell Interrupt Service Routines (ISR).
    Interrupt_initVectorTable();
    // board.c and board.h generate by sysconfig
    Board_init();

    // Disable sync and clock to PWM
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    // Configure COMP1H
    init_cmpss(CMPSS1_BASE);
    init_cmpss(CMPSS2_BASE);
    init_cmpss(CMPSS3_BASE);
    // initEPWM1 - Configure ePWM1
    float tbclk = init_EPWM(myEPWM1_BASE);
    // initEPWM2 - Configure ePWM2
    tbclk = init_EPWM(myEPWM2_BASE);
    // Configure phase between PWM1 & PWM2. PWM1 is configure as master and ePWM2 as slaves.
    EPWM_disablePhaseShiftLoad(myEPWM1_BASE);
    EPWM_setPhaseShift(myEPWM1_BASE, 0U);
    // ePWM1 SYNCO is generated on CTR=0
    EPWM_enableSyncOutPulseSource(myEPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);

    // Configure phase shift for EPWM2 & 3
    set_phase(myEPWM2_BASE, PHI);
    EPWM_setSyncInPulseSource(myEPWM2_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    EPWM_enablePhaseShiftLoad(myEPWM2_BASE);

    // Calculate delays
    get_delays_FED_RED(myEPWM1_BASE, tbclk);
    get_delays_FED_RED(myEPWM2_BASE, tbclk);

    // Enable sync and clock to PWM
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    // Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
    EINT;
    ERTM;

    while(1)
    {
        // Trip flag is set when CTRIP signal is asserted
        if((EPWM_getTripZoneFlagStatus(myEPWM1_BASE) & EPWM_TZ_FLAG_OST) != 0U && (EPWM_getTripZoneFlagStatus(myEPWM2_BASE) & EPWM_TZ_FLAG_OST) != 0U)
        {
            // Wait for comparator CTRIP to de-assert
            while((CMPSS_getStatus(CMPSS1_BASE) & CMPSS_STS_HI_FILTOUT) != 0U && (CMPSS_getStatus(CMPSS2_BASE) & CMPSS_STS_HI_FILTOUT) != 0U)
            {
            }
            // Clear trip flags
            EPWM_clearTripZoneFlag(myEPWM1_BASE, EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_OST);
            EPWM_clearTripZoneFlag(myEPWM2_BASE, EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_OST);
        }
    }
}

float init_EPWM(base)
{
    float PWM_TBPRD;
    float PWM_CMPA;
    EPWM_ClockDivider PWM_PARAM_PRESCALER;
    EPWM_HSClockDivider PWM_PARAM_HIGHSPEEDPRESCALER;
    float TBCLK;

    get_pwm_clock_from_freq(&PWM_TBPRD , &PWM_CMPA , &PWM_PARAM_PRESCALER , &PWM_PARAM_HIGHSPEEDPRESCALER, &TBCLK);

    // Parameters
    EPWM_setTimeBasePeriod(base, (uint16_t)PWM_TBPRD);
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, (uint16_t)PWM_CMPA);
    EPWM_setPhaseShift(base, 0U);
    EPWM_setTimeBaseCounter(base, 0U);
    EPWM_setTimeBaseCounterMode(base, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_disablePhaseShiftLoad(base);
    EPWM_setClockPrescaler(base, PWM_PARAM_PRESCALER, PWM_PARAM_HIGHSPEEDPRESCALER);

    // Set up shadowing
    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);

    // Set actions
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

    // Trip zone
    // Configure ePWM1x to output low on TZx TRIP
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);
    // Trigger event when DCBH is high
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);
    // Configure DCBH to use TRIP4 as an input
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN4, EPWM_DC_TYPE_DCBH);
    // Enable DCB as OST
    EPWM_enableTripZoneSignals(base, EPWM_TZ_SIGNAL_DCBEVT1);
    // Configure the DCB path to be unfiltered and asynchronous
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);

    // To use CMPx_LP
    //AIO224 -> myAIO0 Pinmux
    GPIO_setPinConfig(GPIO_226_GPIO226);
    //AIO237 -> myAIO0 Pinmux
    GPIO_setPinConfig(GPIO_237_GPIO237);
    //AIO226 -> myAIO2 Pinmux
    GPIO_setPinConfig(GPIO_230_GPIO230);
    // To use CMP1_HP0
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_1, 1);
    // To use CMP2_HN1
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_2, 3);
    // To use CMP3_HP0
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_3, 0);

    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX01_CMPSS1_CTRIPL);
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX03_CMPSS2_CTRIPL);
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX05_CMPSS3_CTRIPL);

    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX01 | XBAR_MUX03 | XBAR_MUX05);

    // Clear trip flags
    EPWM_clearTripZoneFlag(base, EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_OST);
    return TBCLK;
}

void set_delays(uint32_t base, uint16_t DBFED, uint16_t DBRED)
{
    // Sets up the rising edge delay input signal.
    EPWM_setFallingEdgeDeadBandDelayInput(base, EPWM_DB_INPUT_EPWMA);
    // Sets up the falling edge delay input signal.
    EPWM_setRisingEdgeDeadBandDelayInput(base, EPWM_DB_INPUT_EPWMA);
    // This function sets the FED count value, this one should be less than 16384.
    EPWM_setFallingEdgeDelayCount(base, DBFED);
    // This function sets the RED count value, this one should be less than 16384.
    EPWM_setRisingEdgeDelayCount(base, DBRED);
    // This function sets up the polarity : EPWM_DB_POLARITY_ACTIVE_HIGH => polarity is not inverted and EPWM_DB_POLARITY_ACTIVE_LOW => polarity is inverted.
    EPWM_setDeadBandDelayPolarity(base, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(base, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    // This function sets up the dead band delay mode. The enableDelayMode determines if a dead band delay should be applied.
    EPWM_setDeadBandDelayMode(base, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(base, EPWM_DB_FED, true);
    //EPWM_setDeadBandOutputSwapMode(myEPWM2_BASE, EPWM_DB_OUTPUT_A, false);
    EPWM_setDeadBandOutputSwapMode(base, EPWM_DB_OUTPUT_B, false);
}

void init_cmpss(base)
{
    // Enable CMPSS and configure the negative input signal to come from the DAC
    CMPSS_enableModule(base);
    CMPSS_configHighComparator(base, CMPSS_INSRC_DAC);
    CMPSS_configLowComparator(base, CMPSS_INSRC_DAC);
    // Use VDDA as the reference for the DAC and set DAC value to midpoint for arbitrary reference.
    CMPSS_configDAC(base, CMPSS_DACREF_VDDA | CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);
    CMPSS_setDACValueHigh(base, 1024);
    // Configure the output signals. Both CTRIPH will be fed by the synchronous comparator output.
    CMPSS_configOutputsHigh(base, CMPSS_TRIP_SYNC_COMP);
    CMPSS_configOutputsLow(base, CMPSS_TRIP_SYNC_COMP);
}

    CMPSS_setDACValueHigh(base, 1024);