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器件型号：TMS320F28388D 主题中讨论的其他器件：C2000WARE
勘误表 TMS320F2838x 实时 MCU 器件勘误表 器件修订版本 A、0
通报存储器：有效存储器之外的预取
闪存中提到了它–预取队列深度为16个 x16字。
但在 表3-1中。 受通报影响的存储器-闪存(0x000B FFF8-0x000B FFFF)为8字深度。
请澄清。
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勘误表 TMS320F2838x 实时 MCU 器件勘误表 器件修订版本 A、0
通报存储器：有效存储器之外的预取
闪存中提到了它–预取队列深度为16个 x16字。
但在 表3-1中。 受通报影响的存储器-闪存(0x000B FFF8-0x000B FFFF)为8字深度。
请澄清。
Tarun、
这意味着、如果该段用于程序代码、则在链接器.cmd 文件中、对于闪存存储器、您应该从分配中排除地址0xBFFF8-0xBFFFF (在闪存扇区13中)。 如果存储器用于数据存储、则没有此类限制。
在任何使用闪存存储程序代码的示例中、我们都在 C2000Ware 示例中的.cmd 文件中处理了上述内容
我用 C/P 来显示2838x_flash_lnk_cpu1.cmd 以下内容(在目录路径 C：\ti\c2000\C2000Ware_3_04_00_00\device_support\f2838x\con\cmd)：
MEMORY
{
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B1, length = 0x00024F
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD0 : origin = 0x00C000, length = 0x000800
RAMD1 : origin = 0x00C800, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00D000, length = 0x001000
RAMGS1 : origin = 0x00E000, length = 0x001000
RAMGS2 : origin = 0x00F000, length = 0x001000
RAMGS3 : origin = 0x010000, length = 0x001000
RAMGS4 : origin = 0x011000, length = 0x001000
RAMGS5 : origin = 0x012000, length = 0x001000
RAMGS6 : origin = 0x013000, length = 0x001000
RAMGS7 : origin = 0x014000, length = 0x001000
RAMGS8 : origin = 0x015000, length = 0x001000
RAMGS9 : origin = 0x016000, length = 0x001000
RAMGS10 : origin = 0x017000, length = 0x001000
RAMGS11 : origin = 0x018000, length = 0x001000
RAMGS12 : origin = 0x019000, length = 0x001000
RAMGS13 : origin = 0x01A000, length = 0x001000
RAMGS14 : origin = 0x01B000, length = 0x001000
RAMGS15 : origin = 0x01C000, length = 0x000FF8
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* Flash sectors */
FLASH0 : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASH13 : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
// FLASH13_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
CPUTOCMRAM : origin = 0x039000, length = 0x000800
CMTOCPURAM : origin = 0x038000, length = 0x000800
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
}
SECTIONS
{
codestart : > BEGIN, ALIGN(8)
.text : >> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(8)
.cinit : > FLASH4, ALIGN(8)
.switch : > FLASH1, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM1
#if defined(__TI_EABI__)
.init_array : > FLASH1, ALIGN(8)
.bss : > RAMLS5
.bss:output : > RAMLS3
.bss:cio : > RAMLS5
.data : > RAMLS5
.sysmem : > RAMLS5
/* Initalized sections go in Flash */
.const : > FLASH5, ALIGN(8)
#else
.pinit : > FLASH1, ALIGN(8)
.ebss : > RAMLS5
.esysmem : > RAMLS5
.cio : > RAMLS5
/* Initalized sections go in Flash */
.econst : >> FLASH4 | FLASH5, ALIGN(8)
#endif
ramgs0 : > RAMGS0, type=NOINIT
ramgs1 : > RAMGS1, type=NOINIT
MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
MSGRAM_CPU_TO_CM : > CPUTOCMRAM, type=NOINIT
MSGRAM_CM_TO_CPU : > CMTOCPURAM, type=NOINIT
/* The following section definition are for SDFM examples */
Filter_RegsFile : > RAMGS0
Filter1_RegsFile : > RAMGS1, fill=0x1111
Filter2_RegsFile : > RAMGS2, fill=0x2222
Filter3_RegsFile : > RAMGS3, fill=0x3333
Filter4_RegsFile : > RAMGS4, fill=0x4444
Difference_RegsFile : >RAMGS5, fill=0x3333
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASH3,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASH3,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
ALIGN(8)
#endif
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
最棒的
Matthew