[参考译文] TMS320F280025C：优先级中断(ADC 和其他)

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https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1158288/tms320f280025c-priority-interrupt-adc-and-others

器件型号：TMS320F280025C
主题中讨论的其他器件：C2000WARE

您好！

我遇到了一个问题、想要更改中断优先级、因此我在项目中包含了相应的头文件。您可以在此处找到详细信息。中断可以独立工作(我对它们进行了注释、然后在主程序中逐一重新激活它们)、但当我至少激活其中的两个中断时、它们将不再工作。例如、当我激活 ADC 中断并减慢任务时、我不再转至 ADC 中断。

我查看过这些示例、但找不到解决方案。

Here a part of my main code

/**
 * Interrupt for state machine sequencing and synchronization for slow background tasks all of 10ms.
 */
timer_cpu_config(CPUTIMER0_BASE, DEVICE_SYSCLK_FREQ, 10000);
Interrupt_register(INT_TIMER0, &isr_slow_tasks);
CPUTimer_enableInterrupt(CPUTIMER0_BASE);
Interrupt_enable(INT_TIMER0);

/**
 * Set up the ADC / ePWM SOC and initialize the end of conversion.
 * Enable interrupt.
 */
Interrupt_register(INT_ADCA1, &isr_adca);
adc_config(ADCA_BASE);
adc_config(ADCC_BASE);
adc_init_soc();
Interrupt_enable(INT_ADCA1);

/**
 * Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
 */
EINT;
ERTM;

__interrupt void isr_adca(void)
{
    GPIO_writePin(4, 1); // for test

    /// Save IER register on stack
    volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);

    /// See prioritized_isr_levels.h file for explanations and details. Set global priority with INTxPL values and others Gx_xPL
    /// Set the global and group priority to allow CPU interrupts with higher priority.
    /// The user must set the appropriate priority level for each of the CPU interrupts.
    /// This is termed as the "global" priority. The priority level must be a number between 1 (highest) to 16 (lowest).
    /// A value of 0 must be entered for reserved interrupts or interrupts that are not used.
    IER |= M_INT1;
    IER &= MINT1;
    HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_1;

    /// Enable Interrupts
    Interrupt_clearACKGroup(0xFFFFU);
    __asm("  NOP");
    EINT;

    /// To be sure all contactor's are open when offsets are read in order to obtain the correct value of the offset
    if((flag_read_offset_adca == 0) &&
       (flag_read_offset_adcc == 0) &&
       (engineer_return_contactor_k_line_fc == RETURN_CONTACTOR_OPEN) &&
       (engineer_return_contactor_k_pl_fc == RETURN_CONTACTOR_OPEN) &&
       (engineer_return_contactor_k_line_batt == RETURN_CONTACTOR_OPEN) &&
       (engineer_return_contactor_k_pl_batt == RETURN_CONTACTOR_OPEN))
    {
        read_offset_at_init_adca();
        flag_read_offset_adca = 1;
        read_offset_at_init_adcc();
        flag_read_offset_adcc = 1;
    }

    MU_TRAC_BATT_FLT_ACC_SAMPLE = ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER0) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER1) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER2) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER3);
    /// Divide by 4 to obtain average value.
    MU_TRAC_BATT_FLT_AVG_SAMPLE = (MU_TRAC_BATT_FLT_ACC_SAMPLE >> 2);

    MU_FUEL_CELL_FLT_ACC_SAMPLE = ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER0) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER1) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER2) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER3);
    /// Divide by 4 to obtain average value.
    MU_FUEL_CELL_FLT_AVG_SAMPLE = (MU_FUEL_CELL_FLT_ACC_SAMPLE >> 2);

    MI_L_U_FLT_ACC_SAMPLE = ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER4) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER5) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER6) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER7);
    /// Divide by 4 to obtain average value.
    MI_L_U_FLT_AVG_SAMPLE = (MI_L_U_FLT_ACC_SAMPLE >> 2);

    MI_L_V_FLT_ACC_SAMPLE = ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER4) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER5) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER6) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER7);
    /// Divide by 4 to obtain average value.
    MI_L_V_FLT_AVG_SAMPLE = (MI_L_V_FLT_ACC_SAMPLE >> 2);

    MI_L_W_FLT_ACC_SAMPLE = ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER8) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER9) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER10) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER11);
    /// Divide by 4 to obtain average value.
    MI_L_W_FLT_AVG_SAMPLE = (MI_L_W_FLT_ACC_SAMPLE >> 2);

    MI_TRAC_BATT_FLT_ACC_SAMPLE = ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER8) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER9) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER10) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER11);
    /// Divide by 4 to obtain average value.
    MI_TRAC_BATT_FLT_AVG_SAMPLE = (MI_TRAC_BATT_FLT_ACC_SAMPLE >> 2);

    MU_FUEL_CELL_PCH_FLT_ACC_SAMPLE = ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER12) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER13);
    /// Divide by 2 to obtain average value.
    MU_FUEL_CELL_PCH_FLT_AVG_SAMPLE = (MU_FUEL_CELL_PCH_FLT_ACC_SAMPLE >> 1);

    MU_TRAC_BATT_FLT_ACC_SAMPLE = ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER12) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER13);
    /// Divide by 2 to obtain average value.
    MU_TRAC_BATT_PCH_FLT_AVG_SAMPLE = (MU_TRAC_BATT_FLT_ACC_SAMPLE >> 1);

    REF_MI_H_2V5_ACC_SAMPLE = ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER14) + ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER15);
    /// Divide by 2 to obtain average value.
    REF_MI_H_2V5_AVG_SAMPLE = (REF_MI_H_2V5_ACC_SAMPLE >> 1);

    MT_COLD_PLATE_FLT_ACC_SAMPLE = ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER14) + ADC_readResult(ADCCRESULT_BASE, ADC_SOC_NUMBER15);
    /// Divide by 2 to obtain average value.
    MT_COLD_PLATE_FLT_AVG_SAMPLE = (MT_COLD_PLATE_FLT_ACC_SAMPLE >> 1);

    /// Check if overflow has occurred
    if(ADC_getInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1) == true)
    {
        ADC_clearInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1);
        ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);
    }
    /// Clear the interrupt flag
    ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);
    /// Acknowledge the interrupt, see PIE Interrupt Vectors table
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
    /// Disable interrupts and restore registers saved:
    DINT;
    HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;

    GPIO_writePin(4, 0); // for test
}

__interrupt void isr_slow_tasks()
{
    GPIO_writePin(39, 1); // for test

    /// Save IER register on stack
    volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);
    /// Set the global and group priority to allow CPU interrupts with higher priority
    IER |= M_INT1;
    IER &= MINT1;
    HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_7;

    /// Enable Interrupts
    Interrupt_clearACKGroup(0xFFFFU);
    __asm("  NOP");
    EINT;

    if(CPUTimer_getTimerOverflowStatus(CPUTIMER0_BASE) == true)
    {
        CPUTimer_clearOverflowFlag(CPUTIMER0_BASE);
    }

    /// Update data and send frames if CAN request is detected.
    can_request();
    /// Read engineer variables and if request by user's is detected.
    engineer_variable_and_request_forcing();
    /// CMPSS monitoring to detect if protection is set.
    cmpss_and_cold_plate_monitoring();
    /// Driver return monitoring to detect if protection is set.
    drv_monitoring();
    /// See requirement REQ_SYST0038
    //detection_coldplate(cold_plate_pin, &cold_plate_detect, &cold_plate_state_error, &cold_plate_state);
    /// See requirement REQ_SYST0039
    //detection_contactor(&k_line_batt, &k_line_batt_state_error, &trigger_state_kline_batt, &trigger_flag_kline_batt, &untrigger_flag_kline_batt);
    /// See requirement REQ_SYST0040
    //detection_contactor(&k_line_fuel_cell, &k_line_fc_state_error, &trigger_state_kline_fc, &trigger_flag_klinefc, &untrigger_flag_klinefc);
    /// See requirement REQ_SYST0041
    //detection_contactor(&k_pl_batt, &k_pl_batt_state_error, &trigger_state_kpl_batt, &trigger_flag_kpl_batt, &untrigger_flag_kpl_batt );
    /// See requirement REQ_SYST0042
    //detection_contactor(&k_pl_fuel_cell, &k_pl_fc_state_error, &trigger_state_kpl_fc, &trigger_flag_kpl_fc, &untrigger_flag_kpl_fc);
    /// Get authorization for open contactor's if converter's are off since delay.
    get_open_contactor_authorization(&open_contactor, &ack_inh_converter, &open_contactor_authorization);
    /// Get authorization for close contactor's if converter's are off since delay and no monitoring are activate.
    get_close_k_pl_contactor_authorization(&close_contactor, &step_global, &close_k_pl_authorization);
    /// Actions at the state machine due to detection at the contactor's.
    contactor_monitoring();
    /// State machine
    sm_main();
    /// Detect if a request to exit RUN state is detected (stop or no loop choice or vehicle crash is nok or consign < min).
    request_to_exit_run_state();

    /// Acknowledge the interrupt, see PIE Interrupt Vectors table
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
    /// Disable interrupts and restore registers saved:
    DINT;
    HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;

    GPIO_writePin(39, 0); // for test
}

#ifndef PRIORITIZED_ISR_LEVELS_H
#define PRIORITIZED_ISR_LEVELS_H

#ifdef __cplusplus
extern "C" {
#endif

//
// Include the header file with software interrupt prioritization logic
//
#include "sw_interrupt_prioritization_logic.h"

//
// Mask for interrupt groups
//
#define M_INT1      0x0001  // INT1 Mask
#define M_INT2      0x0002  // INT2 Mask
#define M_INT3      0x0004  // INT3 Mask
#define M_INT4      0x0008  // INT4 Mask
#define M_INT5      0x0010  // INT5 Mask
#define M_INT6      0x0020  // INT6 Mask
#define M_INT7      0x0040  // INT7 Mask
#define M_INT8      0x0080  // INT8 Mask
#define M_INT9      0x0100  // INT9 Mask
#define M_INT10     0x0200  // INT10 Mask
#define M_INT11     0x0400  // INT11 Mask
#define M_INT12     0x0800  // INT12 Mask
#define M_INT13     0x1000  // INT13 Mask
#define M_INT14     0x2000  // INT14 Mask
#define M_DLOG      0x4000  // DLOGINT Mask
#define M_RTOS      0x8000  // RTOSINT Mask

//
// Interrupt Enable Register Allocation:
// Interrupts can be enabled/disabled using the CPU interrupt enable register
// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12).
//

//
// Set "Global" Interrupt Priority Level (IER register):
//
// The user must set the appropriate priority level for each of the CPU
// interrupts. This is termed as the "global" priority. The priority level
// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
// be entered for reserved interrupts or interrupts that are not used.
//
// Note: The priority levels below are used to calculate the IER register
//       interrupt masks MINT1 to MINT16.
//
// Note: The priority levels shown here may not make sense in a
//       real application.  This is for demonstration purposes only!!!
//
//       The user should change these to values that make sense for
//       their application.
//
// 0  = not used
// 1  = highest priority
// ...
// 16 = lowest priority
//
#define INT1PL      3        // Global Priority for Group1 Interrupts
#define INT2PL      1        // Global Priority for Group2 Interrupts
#define INT3PL      2        // Global Priority for Group3 Interrupts
#define INT4PL      0        // Global Priority for Group4 Interrupts
#define INT5PL      0        // Global Priority for Group5 Interrupts
#define INT6PL      0        // Global Priority for Group6 Interrupts
#define INT7PL      0        // Global Priority for Group7 Interrupts
#define INT8PL      0        // Global Priority for Group8 Interrupts
#define INT9PL      0        // Global Priority for Group9 Interrupts
#define INT10PL     0        // Global Priority for Group10 Interrupts
#define INT11PL     0        // Global Priority for Group11 Interrupts
#define INT12PL     0        // Global Priority for Group12 Interrupts
#define INT13PL     0        // Global Priority for INT13 (TINT1)
#define INT14PL     0        // Global Priority for INT14 (TINT2)
#define INT15PL     0        // Global Priority for DATALOG
#define INT16PL     0        // Global Priority for RTOSINT

//
// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers):
//
// The user must set the appropriate priority level for each of the PIE
// interrupts. This is termed as the "group" priority. The priority level
// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
// be entered for reserved interrupts or interrupts that are not used.
//
// Note: The priority levels below are used to calculate the following
//       PIEIER register interrupt masks:
//       MG1_1 to MG1_16
//       MG2_1 to MG2_16
//       MG3_1 to MG3_16
//       MG4_1 to MG4_16
//       MG5_1 to MG5_16
//       MG6_1 to MG6_16
//       MG7_1 to MG7_16
//       MG8_1 to MG8_16
//       MG9_1 to MG9_16
//       MG10_1 to MG10_16
//       MG11_1 to MG11_16
//       MG12_1 to MG12_16
//
// Note: The priority levels shown here may not make sense in a
//       real application.  This is for demonstration purposes only!!!
//
//       The user should change these to values that make sense for
//       their application.
//
// 0  = not used
// 1  = highest priority
// ...
// 16  = lowest priority
//
#define G1_1PL      1       // ADCA1_INT
#define G1_2PL      0       // Reserved
#define G1_3PL      0       // ADCC1_INT
#define G1_4PL      0       // XINT1_INT
#define G1_5PL      0       // XINT2_INT
#define G1_6PL      0       // Reserved
#define G1_7PL      2       // TIMER0_INT
#define G1_8PL      0       // WAKE_INT
#define G1_9PL      0       // Reserved
#define G1_10PL     0       // Reserved
#define G1_11PL     0       // Reserved
#define G1_12PL     0       // Reserved
#define G1_13PL     0       // Reserved
#define G1_14PL     0       // Reserved
#define G1_15PL     0       // Reserved
#define G1_16PL     0       // Reserved

#define G2_1PL      1       // EPWM1_TZ_INT
#define G2_2PL      2       // EPWM2_TZ_INT
#define G2_3PL      0       // EPWM3_TZ_INT
#define G2_4PL      3       // EPWM4_TZ_INT
#define G2_5PL      0       // EPWM5_TZ_INT
#define G2_6PL      0       // EPWM6_TZ_INT
#define G2_7PL      0       // EPWM7_TZ_INT
#define G2_8PL      0       // Reserved
#define G2_9PL      0       // Reserved
#define G2_10PL     0       // Reserved
#define G2_11PL     0       // Reserved
#define G2_12PL     0       // Reserved
#define G2_13PL     0       // Reserved
#define G2_14PL     0       // Reserved
#define G2_15PL     0       // Reserved
#define G2_16PL     0       // Reserved

#define G3_1PL      0       // EPWM1_INT
#define G3_2PL      0       // EPWM2_INT
#define G3_3PL      1       // EPWM3_INT
#define G3_4PL      0       // EPWM4_INT
#define G3_5PL      0       // EPWM5_INT
#define G3_6PL      0       // EPWM6_INT
#define G3_7PL      0       // EPWM7_INT
#define G3_8PL      0       // Reserved
#define G3_9PL      0       // Reserved
#define G3_10PL     0       // Reserved
#define G3_11PL     0       // Reserved
#define G3_12PL     0       // Reserved
#define G3_13PL     0       // Reserved
#define G3_14PL     0       // Reserved
#define G3_15PL     0       // Reserved
#define G3_16PL     0       // Reserved

#define G4_1PL      0       // ECAP1_INT
#define G4_2PL      0       // ECAP2_INT
#define G4_3PL      0       // ECAP3_INT
#define G4_4PL      0       // Reserved
#define G4_5PL      0       // Reserved
#define G4_6PL      0       // Reserved
#define G4_7PL      0       // Reserved
#define G4_8PL      0       // Reserved
#define G4_9PL      0       // Reserved
#define G4_10PL     0       // Reserved
#define G4_11PL     0       // ECAP3_2_INT
#define G4_12PL     0       // Reserved
#define G4_13PL     0       // Reserved
#define G4_14PL     0       // Reserved
#define G4_15PL     0       // Reserved
#define G4_16PL     0       // Reserved

#define G5_1PL      0       // EQEP1_INT
#define G5_2PL      0       // EQEP2_INT
#define G5_3PL      0       // Reserved
#define G5_4PL      0       // Reserved
#define G5_5PL      0       // CLB1_INT
#define G5_6PL      0       // CLB2_INT
#define G5_7PL      0       // Reserved
#define G5_8PL      0       // Reserved
#define G5_9PL      0       // Reserved
#define G5_10PL     0       // Reserved
#define G5_11PL     0       // Reserved
#define G5_12PL     0       // Reserved
#define G5_13PL     0       // Reserved
#define G5_14PL     0       // Reserved
#define G5_15PL     0       // Reserved
#define G5_16PL     0       // Reserved

#define G6_1PL      0       // SPIA_RX_INT
#define G6_2PL      0       // SPIA_TX_INT
#define G6_3PL      0       // SPIB_RX_INT
#define G6_4PL      0       // SPIB_TX_INT
#define G6_5PL      0       // Reserved
#define G6_6PL      0       // Reserved
#define G6_7PL      0       // Reserved
#define G6_8PL      0       // Reserved
#define G6_9PL      0       // Reserved
#define G6_10PL     0       // Reserved
#define G6_11PL     0       // Reserved
#define G6_12PL     0       // Reserved
#define G6_13PL     0       // Reserved
#define G6_14PL     0       // Reserved
#define G6_15PL     0       // Reserved
#define G6_16PL     0       // Reserved

#define G7_1PL      0       // DMA_CH1_INT
#define G7_2PL      0       // DMA_CH2_INT
#define G7_3PL      0       // DMA_CH3_INT
#define G7_4PL      0       // DMA_CH4_INT
#define G7_5PL      0       // DMA_CH5_INT
#define G7_6PL      0       // DMA_CH6_INT
#define G7_7PL      0       // Reserved
#define G7_8PL      0       // Reserved
#define G7_9PL      0       // Reserved
#define G7_10PL     0       // Reserved
#define G7_11PL     0       // FSITXA1_INT
#define G7_12PL     0       // FSITXA2_INT
#define G7_13PL     0       // FSIRXA1_INT
#define G7_14PL     0       // FSIRXA2_INT
#define G7_15PL     0       // Reserved
#define G7_16PL     0       // DCC0_INT

#define G8_1PL      0       // I2CA_INT
#define G8_2PL      0       // I2CA_FIFO_INT
#define G8_3PL      0       // I2CB_INT
#define G8_4PL      0       // I2CB_FIFO_INT
#define G8_5PL      0       // Reserved
#define G8_6PL      0       // Reserved
#define G8_7PL      0       // Reserved
#define G8_8PL      0       // Reserved
#define G8_9PL      0       // LINA0_INT
#define G8_10PL     0       // LINA1_INT
#define G8_11PL     0       // LINB0_INT
#define G8_12PL     0       // LINB1_INT
#define G8_13PL     0       // PMBUSA_INT
#define G8_14PL     0       // Reserved
#define G8_15PL     0       // Reserved
#define G8_16PL     0       // DCC1_INT

#define G9_1PL      0       // SCIA_RX_INT
#define G9_2PL      0       // SCIA_TX_INT
#define G9_3PL      0       // Reserved
#define G9_4PL      0       // Reserved
#define G9_5PL      0       // CANA0_INT
#define G9_6PL      0       // CANA1_INT
#define G9_7PL      0       // Reserved
#define G9_8PL      0       // Reserved
#define G9_9PL      0       // Reserved
#define G9_10PL     0       // Reserved
#define G9_11PL     0       // Reserved
#define G9_12PL     0       // Reserved
#define G9_13PL     0       // BGCRC_INT
#define G9_14PL     0       // Reserved
#define G9_15PL     0       // Reserved
#define G9_16PL     0       // HICA_INT

#define G10_1PL     0       // ADCA_EVT_INT
#define G10_2PL     0       // ADCA2_INT
#define G10_3PL     0       // ADCA3_INT
#define G10_4PL     0       // ADCA4_INT
#define G10_5PL     0       // Reserved
#define G10_6PL     0       // Reserved
#define G10_7PL     0       // Reserved
#define G10_8PL     0       // Reserved
#define G10_9PL     0       // ADCC_EVT_INT
#define G10_10PL    0       // ADCC2_INT
#define G10_11PL    0       // ADCC3_INT
#define G10_12PL    0       // ADCC4_INT
#define G10_13PL    0       // Reserved
#define G10_14PL    0       // Reserved
#define G10_15PL    0       // Reserved
#define G10_16PL    0       // Reserved

#define G11_1PL     0       // Reserved
#define G11_2PL     0       // Reserved
#define G11_3PL     0       // Reserved
#define G11_4PL     0       // Reserved
#define G11_5PL     0       // Reserved
#define G11_6PL     0       // Reserved
#define G11_7PL     0       // Reserved
#define G11_8PL     0       // Reserved
#define G11_9PL     0       // Reserved
#define G11_10PL    0       // Reserved
#define G11_11PL    0       // Reserved
#define G11_12PL    0       // Reserved
#define G11_13PL    0       // Reserved
#define G11_14PL    0       // Reserved
#define G11_15PL    0       // Reserved
#define G11_16PL    0       // Reserved

#define G12_1PL     0       // XINT3_INT
#define G12_2PL     0       // XINT4_INT
#define G12_3PL     0       // XINT5_INT
#define G12_4PL     0       // PBIST_INT
#define G12_5PL     0       // FMC_INT
#define G12_6PL     0       // Reserved
#define G12_7PL     0       // FPU_OVERFLOW_ISR
#define G12_8PL     0       // FPU_UNDERFLOW_ISR
#define G12_9PL     0       // Reserved
#define G12_10PL    0       // RAM_CORRECTABLE_ERROR_ISR
#define G12_11PL    0       // FLASH_CORRECTABLE_ERROR_ISR
#define G12_12PL    0       // RAM_ACCESS_VIOLATION_INT
#define G12_13PL    0       // SYS_PLL_SLIP_INT
#define G12_14PL    0       // Reserved
#define G12_15PL    0       // Reserved
#define G12_16PL    0       // Reserved

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif

可能是一个糟糕的环境？可以帮帮我吗？

谢谢

Damien

3 年多前

0 admin 3 年多前

TI__Guru**** 2411640 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Damien：

感谢您的提问。对于这种情况、我强烈建议单步执行代码并查找代码卡住的位置。我最想的是、启用的中断之一是"使另一个中断无法运行。基本上、它会持续中断较高的优先级、并防止另一个中断触发。

另一种可能是一个中断重复中断自身：进入 ISR、开始处理、但随后为自身接收另一个中断并重新开始、并反复重复。

通过单步执行代码可以轻松诊断这两种情况。

为了继续提供帮助、您能否单步执行代码并提供代码中"卡住"的部分的代码片段？

此致、

Vince

0 admin 3 年多前

TI__Guru**** 2411640 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Vince：

感谢您的回复。

在执行各种测试后、我将两个中断配置为 ADCA1和 TIMER0、我希望 TIMER0中断具有比 ADC 更高的优先级、因此我相应地修改了头文件。我还将我的两个中断连接到示波器上、因为一旦 ADC 中断不再激活、TIMER0中断必须每10ms 发生一次、所以我们观察到的情况是、这两个中断在开始时运行不良。

我的问题似乎来自优先级上的 ADC 中断？

当我在代码中注释此中断时，为什么 PIEIFR3.INTx3位处于活动状态？

//中断寄存器(INT_EPWM3、&ISR_regulation)；
//中断_ENABLE (INT_EPWM3)；

And my TIMER0 interrupt :

__interrupt void isr_slow_tasks()
{
    GPIO_writePin(39, 1); // for test

    /// See the C28x interrupt nesting document for more details.
    /// Save IER register on stack
    volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);
    /// Set the global and group priority to allow CPU interrupts with higher priority.
    /// Modify the IER register to allow CPU interrupts with a higher user priority to be serviced.
    /// At this time IER has already been saved on the stack.
    IER |= M_INT1;
    IER &= MINT1;
    HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_7;

    /// Enable Interrupts
    /// Clear the PIEACK bits.
    Interrupt_clearACKGroup(0xFFFFU);
    /// Wait at least one cycle.
    __asm("  NOP");
    /// Clear the INTM bit. Use this define or the assembly statement asm(" CLRC INTM).
    EINT;

    if(CPUTimer_getTimerOverflowStatus(CPUTIMER0_BASE) == true)
    {
        CPUTimer_clearOverflowFlag(CPUTIMER0_BASE);
    }

    .......

    /// Set the INTM to disable interrupts, use this define or the assembly statement asm("SETC INTM").
    DINT;
    /// Acknowledge the interrupt, see PIE Interrupt Vectors table
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
    /// Restore PIEIER
    HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;

    GPIO_writePin(39, 0); // for test
}

Here my ADC interrupt :

__interrupt void isr_adca(void)
{
    GPIO_writePin(4, 1); // for test

    /// See the C28x interrupt nesting document for more details.
    /// Save IER register on stack
    volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);

    /// Set the global and group priority to allow CPU interrupts with higher priority.
    /// Modify the IER register to allow CPU interrupts with a higher user priority to be serviced.
    /// At this time IER has already been saved on the stack.
    IER |= M_INT1;
    IER &= MINT1;
    HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_1;

    /// Enable Interrupts
    /// Clear the PIEACK bits
    Interrupt_clearACKGroup(0xFFFFU);
    /// Wait at least one cycle.
    __asm("  NOP");
    /// Clear the INTM bit. Use this define or the assembly statement asm(" CLRC INTM).
    EINT;

    .......

    /// Check if overflow has occurred
    if(ADC_getInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1) == true)
    {
        ADC_clearInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1);
        ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);
    }
    /// Clear the interrupt flag
    ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);

    /// Set the INTM to disable interrupts, use this define or the assembly statement asm("SETC INTM").
    DINT;
    /// Acknowledge the interrupt, see PIE Interrupt Vectors table
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
    /// Restore PIEIER
    HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;

    GPIO_writePin(4, 0); // for test
}

我用不同的步骤浏览了 C28嵌套中断文档，但我没有看到与代码有任何差异，您能帮我吗？

谢谢

Damien

0 admin 3 年多前

TI__Guru**** 2411640 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

这里是我的 PIEIFR 寄存器和示波器调试器的屏幕截图

粉色信号：ADC 中断

黄色信号：TIMER0中断

很抱歉出现反射。

0 admin 3 年多前

TI__Guru**** 2411640 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Damien：

感谢您的测试和提供屏幕截图。此问题上的示波器捕获提示、反映在 TIMER0中断中。让我在此处放置有问题的代码：

TIMER0 ISR：

    HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_7;

这在 TIMER0 ISR 内部。基本上、这是"允许来自该中断内部通道7的中断"。问题是这意味着只有 Group1、Channel7可以在 Group1、Channel7内中断。因此、基本而言、这仅允许 TIMER0中断本身。这可能不是您想要的。您可能不希望有任何中断 TIMER0的东西。如果是这样、那么你实际上可以从这个 ISR 中删除所有嵌套。

现在进入 ADC 中断：

ADCA1 ISR：

这与上述问题相同、但仅限于此。以下是有问题的代码：

    HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_1;

这表示"允许来自该中断内部通道1的中断"。同样、这意味着唯一能够中断 ADCA1的事情就是它本身。但是从您所说的内容来看、似乎您希望 ADCA1只允许 CPUTIME0在 ADCA1内部中断。如果是、则可以将上面的行更改为：

    HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_7;

现在的内容是"允许来自该中断内部通道7的中断"。或者用另一种方法说："允许来自 ADCA1中断内部 TIMER0的中断"。

此致、

Vince

0 admin 3 年多前

TI__Guru**** 2411640 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Vince：

非常感谢您的澄清、我想更好地解释一下我要做的事情：
我希望设立一项规例：
-在 ADC 中断结束后立即处理 ISR_regulation 中断。
-如果发生 TIMER0中断、则在前两个中断(ISR_ADC 和 ISR_regulation)之后进行处理
最后、如果发生一个 tz 中断、它应该具有比所有其它中断优先级更高的优先级。
我在所有这些方面都迷路了、使用示波器、我还观察到了与之前相同的现象。我无法正确配置优先级和 HW_REG()函数。
可以帮帮我吗？非常感谢

我加入我的代码和屏幕截图：

ISR adc :
__interrupt void isr_adca(void)
{
    GPIO_writePin(4, 1); // for test

    /// See the C28x interrupt nesting document for more details.
    /// Save IER register on stack
    volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);

    /// Set the global and group priority to allow CPU interrupts with higher priority.
    /// Modify the IER register to allow CPU interrupts with a higher user priority to be serviced.
    /// At this time IER has already been saved on the stack.
    IER |= M_INT1;
    IER &= MINT1;

    /// We don't want anything to interrupt ADC interrupt.
    /// ...

    /// Enable Interrupts
    /// Clear the PIEACK bits
    Interrupt_clearACKGroup(0xFFFFU);
    /// Wait at least one cycle.
    __asm("  NOP");
    /// Clear the INTM bit. Use this define or the assembly statement asm(" CLRC INTM).
    EINT;

    ...

    /// Check if overflow has occurred
    if(ADC_getInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1) == true)
    {
        ADC_clearInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1);
        ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);
    }
    /// Clear the interrupt flag
    ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);

    /// Set the INTM to disable interrupts, use this define or the assembly statement asm("SETC INTM").
    DINT;
    /// Acknowledge the interrupt, see PIE Interrupt Vectors table
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
    /// Restore PIEIER
    HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;

    GPIO_writePin(4, 0); // for test
}

__interrupt void isr_slow_tasks()
{
    GPIO_writePin(39, 1); // for test

    /// See the C28x interrupt nesting document for more details.
    /// Save IER register on stack
    volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);
    /// Set the global and group priority to allow CPU interrupts with higher priority.
    /// Modify the IER register to allow CPU interrupts with a higher user priority to be serviced.
    /// At this time IER has already been saved on the stack.
    IER |= M_INT1;
    IER &= MINT1;

    /// Allow interrupts from ADCA1 and regulation (INTEPWM3) inside slow tasks interrupt".
    HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_1;
    HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG3_3;

    /// Enable Interrupts
    /// Clear the PIEACK bits.
    Interrupt_clearACKGroup(0xFFFFU);
    /// Wait at least one cycle.
    __asm("  NOP");
    /// Clear the INTM bit. Use this define or the assembly statement asm(" CLRC INTM).
    EINT;

    if(CPUTimer_getTimerOverflowStatus(CPUTIMER0_BASE) == true)
    {
        CPUTimer_clearOverflowFlag(CPUTIMER0_BASE);
    }

    ...

    /// Set the INTM to disable interrupts, use this define or the assembly statement asm("SETC INTM").
    DINT;
    /// Acknowledge the interrupt, see PIE Interrupt Vectors table
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
    /// Restore PIEIER
    HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;

    GPIO_writePin(39, 0); // for test
}

__interrupt void isr_regulation()
{
    GPIO_writePin(44, 1);

    /// Clear INT flag for this interrupt
    EPWM_clearEventTriggerInterruptFlag(SPWM_REGU);
    /// Save IER register on stack
    volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER3);

    /// Set the global and group priority to allow CPU interrupts with higher priority
    IER |= M_INT3;
    IER &= MINT3;

    /// Enable Interrupts
    Interrupt_clearACKGroup(0xFFFFU);
    __asm("  NOP");
    EINT;

    ...

    /// Acknowledge interrupt group
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP3);
    /// Disable interrupts and restore registers saved:
    DINT;
    HWREGH(PIECTRL_BASE + PIE_O_IER3) = tempPIEIER;

    GPIO_writePin(44, 0);
}

黄色信号：TIMER0中断(缓慢监控)

粉色信号：ADC 中断

蓝色信号：调节中断(INTEPWM3)

如果我可以用时基对其进行总结、我希望在调节中断处理(INTePWM3)之后和 TIMER0中断处理(缓慢监控)之后进行 ADC 中断处理。有可能吗？如何做到这一点？

非常感谢

Damien

0 admin 3 年多前

TI__Guru**** 2411640 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

这里是优先级头文件配置：

#ifndef PRIORITIZED_ISR_LEVELS_H
#define PRIORITIZED_ISR_LEVELS_H

#ifdef __cplusplus
extern "C" {
#endif

#define INT1PL      2        // Global Priority for Group1 Interrupts
#define INT2PL      1        // Global Priority for Group2 Interrupts
#define INT3PL      3        // Global Priority for Group3 Interrupts
#define INT4PL      0        // Global Priority for Group4 Interrupts
#define INT5PL      0        // Global Priority for Group5 Interrupts
#define INT6PL      0        // Global Priority for Group6 Interrupts
#define INT7PL      0        // Global Priority for Group7 Interrupts
#define INT8PL      0        // Global Priority for Group8 Interrupts
#define INT9PL      0        // Global Priority for Group9 Interrupts
#define INT10PL     0        // Global Priority for Group10 Interrupts
#define INT11PL     0        // Global Priority for Group11 Interrupts
#define INT12PL     0        // Global Priority for Group12 Interrupts
#define INT13PL     0        // Global Priority for INT13 (TINT1)
#define INT14PL     0        // Global Priority for INT14 (TINT2)
#define INT15PL     0        // Global Priority for DATALOG
#define INT16PL     0        // Global Priority for RTOSINT


#define G1_1PL      1       // ADCA1_INT
#define G1_2PL      0       // Reserved
#define G1_3PL      0       // ADCC1_INT
#define G1_4PL      0       // XINT1_INT
#define G1_5PL      0       // XINT2_INT
#define G1_6PL      0       // Reserved
#define G1_7PL      2       // TIMER0_INT
#define G1_8PL      0       // WAKE_INT
#define G1_9PL      0       // Reserved
#define G1_10PL     0       // Reserved
#define G1_11PL     0       // Reserved
#define G1_12PL     0       // Reserved
#define G1_13PL     0       // Reserved
#define G1_14PL     0       // Reserved
#define G1_15PL     0       // Reserved
#define G1_16PL     0       // Reserved

#define G2_1PL      1       // EPWM1_TZ_INT
#define G2_2PL      2       // EPWM2_TZ_INT
#define G2_3PL      0       // EPWM3_TZ_INT
#define G2_4PL      3       // EPWM4_TZ_INT
#define G2_5PL      0       // EPWM5_TZ_INT
#define G2_6PL      0       // EPWM6_TZ_INT
#define G2_7PL      0       // EPWM7_TZ_INT
#define G2_8PL      0       // Reserved
#define G2_9PL      0       // Reserved
#define G2_10PL     0       // Reserved
#define G2_11PL     0       // Reserved
#define G2_12PL     0       // Reserved
#define G2_13PL     0       // Reserved
#define G2_14PL     0       // Reserved
#define G2_15PL     0       // Reserved
#define G2_16PL     0       // Reserved

#define G3_1PL      0       // EPWM1_INT
#define G3_2PL      0       // EPWM2_INT
#define G3_3PL      1       // EPWM3_INT
#define G3_4PL      0       // EPWM4_INT
#define G3_5PL      0       // EPWM5_INT
#define G3_6PL      0       // EPWM6_INT
#define G3_7PL      0       // EPWM7_INT
#define G3_8PL      0       // Reserved
#define G3_9PL      0       // Reserved
#define G3_10PL     0       // Reserved
#define G3_11PL     0       // Reserved
#define G3_12PL     0       // Reserved
#define G3_13PL     0       // Reserved
#define G3_14PL     0       // Reserved
#define G3_15PL     0       // Reserved
#define G3_16PL     0       // Reserved


#ifdef __cplusplus
}
#endif /* extern "C" */

#endif

0 admin 3 年多前

TI__Guru**** 2411640 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Damien：

感谢您的跟进。

[引用 userid="489604" URL"~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1158288/tms320f280025c-priority-interrupt-adc-and-others/4357094 #4357094"]-在 ADC 中断结束后立即处理 ISR_regulation 中断。
-如果发生 TIMER0中断、则在前两个中断(ISR_ADC 和 ISR_regulation)之后进行处理
最后、如果发生一个 tz 中断、它应该具有比所有其它中断优先级更高的优先级。 [/报价]

根据这些项目、除了 TZ 中断、嵌套似乎不是任何东西的需要。您提到的其他操作都与顺序操作相关。这意味着、您有一个特定的顺序来处理事情。

我建议从所有其他中断中删除嵌套、除了您尝试在其他中断中发生的中断。提到的每个其他项目似乎都有"在 X 中断之后"的字样。这意味着没有嵌套、而是重新确定优先级。

对于代码、我们通常不会在 E2E 论坛中调试代码转储、因为这样做的支持难度很大。但是、我可以提供以下指针：

1、从去除除1个关键中断之外的所有中断的嵌套和优先级开始。首先尝试使其正常工作。

2.一旦一个嵌套中断正常工作、添加一个额外的中断(嵌套或重新排序、都可以)并使其正常工作。

3.重复此操作，直到所有操作均正常。

此致、

Vince

0 admin 3 年多前

TI__Guru**** 2411640 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Vince：

感谢 Vince 的所有这些经历、我一直隔离各种中断、然后逐一重新激活它们、以便更好地隔离问题。
小问题：嵌套中断意味着什么？因为在某些情况下、优先级管理是不够的？为什么必须在其他中断中声明触发区中断的嵌套？它是最高优先级。

谢谢

Damien

0 admin 3 年多前

TI__Guru**** 2411640 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Damien：

抱歉、我认为我误解了之前的回答。为了实现简单的优先级划分、我建议使用 C2000Ware 中提供的中断优先级划分示例、因为这提供了直接优先级划分的能力。

请告诉我这是否能解答您的问题。

此致、

Vince

C2000™︎ 微控制器（参考译文帖）

C2000™︎ 微控制器（参考译文帖）(Read Only)

[参考译文] TMS320F280025C：优先级中断(ADC 和其他)