Other Parts Discussed in Thread: TMS320F280039
主题中讨论的其他器件:TMS320F280039
问题定义:
使用 CCS 将代码加载到 LAUNCHXL_F280039中、并可以从闪存运行程序。
2.现在,我设计了一个使用80引脚 TMS320F280039处理器的 uC 板。
3.在 cJTAG 模式下使用 LAUNCHXL_F280039、TMS 和 TCK、并在(2)中将相同的代码加载到设计的 uC 板。
看起来代码是从 RAM 而不是从闪存运行的。 这是因为我可以看到加载代码后由 UC 发出的 PWM 信号、但在电源复位后消失。
请帮助、
以下是.cmd 文件:
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
存储器
{
开始:origin = 0x00080000,length = 0x00000002
BOOT_RSVD:origin = 0x00000002,length = 0x00000126
RAMM0:origin = 0x00000128,length = 0x000002D8
RAMM1:origin = 0x00000400,length = 0x000003F8
// RAMM1_RSVD:origin = 0x000007F8,length = 0x00000008 //根据勘误咨询“Memory:Prepetching Beyond valid Memory”(内存:超过有效内存的预取),保留并不用于代码*/
RAMLS0:origin = 0x00008000、length = 0x00000800
RAMLS1:origin = 0x00008800,length = 0x00000800
RAMLS2:origin = 0x00009000,length = 0x00000800
RAMLS3:origin = 0x00009800,length = 0x00000800
RAMLS4:origin = 0x0000A000,length = 0x00000800
RAMLS5:origin = 0x0000A800,length = 0x00000800
RAMLS6:origin = 0x0000B000、length = 0x00000800
RAMLS7:origin = 0x0000B800,length = 0x00000800
RAMGS0:origin = 0x0000C000,length = 0x00001000
RAMGS1:origin = 0x0000D000,length = 0x00001000
RAMGS2:origin = 0x0000E000、length = 0x00001000
RAMGS3:origin = 0x0000F000、length = 0x00000FF8
// RAMGS3_RSVD:origin = 0x0000FFF8,length = 0x00000008 //根据勘误咨询“Memory:Prepetching Beyond valid Memory”(内存:有效内存之外的预取),保留并不用于代码*/
BootROM:origin = 0x003F8000,length = 0x00007FC0
SECURE_ROM:origin = 0x003F2000,length = 0x00006000
复位:origin = 0x003FFFC0,length = 0x00000002
/*闪存扇区*/
/*组0 */
FLASH_BANK0_SEC0:origin = 0x080002、length = 0x000FFE
FLASH_BANK0_SEC1:origin = 0x081000、length = 0x001000
FLASH_BANK0_sec2:origin = 0x082000、length = 0x001000
FLASH_BANK0_SEC3:origin = 0x083000、length = 0x001000
FLASH_BANK0_SEC4:origin = 0x084000、length = 0x001000
FLASH_BANK0_SEC5:origin = 0x085000、length = 0x001000
FLASH_BANK0_SEC6:origin = 0x086000、length = 0x001000
FLASH_BANK0_SEC7:origin = 0x087000、length = 0x001000
FLASH_BANK0_SEC8:origin = 0x088000、length = 0x001000
FLASH_BANK0_SEC9:origin = 0x089000、length = 0x001000
FLASH_BANK0_SEC10:origin = 0x08A000、length = 0x001000
FLASH_BANK0_SEC11:origin = 0x08B000、length = 0x001000
FLASH_BANK0_SEC12:origin = 0x08C000、length = 0x001000
FLASH_BANK0_SEC13:origin = 0x08D000、length = 0x001000
FLASH_BANK0_SEC14:origin = 0x08E000、length = 0x001000
FLASH_BANK0_SEC15:origin = 0x08F000、length = 0x001000
/*银行1 */
FLASH_BANK1_SEC0:origin = 0x090000、length = 0x001000
FLASH_BANK1_SEC1:origin = 0x091000、length = 0x001000
FLASH_BANK1_SEC2:origin = 0x092000,length = 0x001000
FLASH_BANK1_SEC3:origin = 0x093000、length = 0x001000
FLASH_BANK1_SEC4:origin = 0x094000、length = 0x001000
FLASH_BANK1_SEC5:origin = 0x095000、length = 0x001000
FLASH_BANK1_SEC6:origin = 0x096000、length = 0x001000
FLASH_BANK1_SEC7:origin = 0x097000、length = 0x001000
FLASH_BANK1_SEC8:origin = 0x098000、length = 0x001000
FLASH_BANK1_SEC9:origin = 0x099000、length = 0x001000
FLASH_BANK1_SEC10:origin = 0x09A000、length = 0x001000
FLASH_BANK1_SEC11:origin = 0x09B000、length = 0x001000
FLASH_BANK1_SEC12:origin = 0x09C000、length = 0x001000
FLASH_BANK1_SEC13:origin = 0x09D000、length = 0x001000
FLASH_BANK1_SEC14:origin = 0x09E000、length = 0x001000
FLASH_BANK1_SEC15:origin = 0x09F000、length = 0x001000
/*银行2 */
FLASH_Bank2_SEC0:origin = 0x0A0000、length = 0x001000
FLASH_BANK2_SEC1:origin = 0x0A1000、length = 0x001000
FLASH_Bank2_sec2:origin = 0x0A2000、length = 0x001000
FLASH_BANK2_SEC3:origin = 0x0A3000、length = 0x001000
FLASH_BANK2_SEC4:origin = 0x0A4000、length = 0x001000
FLASH_Bank2_SEC5:origin = 0x0A5000、length = 0x001000
FLASH_BANK2_SEC6:origin = 0x0A6000、length = 0x001000
FLASH_BANK2_SEC7:origin = 0x0A7000,length = 0x001000
FLASH_BANK2_SEC8:origin = 0x0A8000、length = 0x001000
FLASH_Bank2_SEC9:origin = 0x0A9000、length = 0x001000
FLASH_BANK2_SEC10:origin = 0x0AA000、length = 0x001000
FLASH_BANK2_SEC11:origin = 0x0AB000、length = 0x001000
FLASH_BANK2_SEC12:origin = 0x0AC000、length = 0x001000
FLASH_BANK2_SEC13:origin = 0x0AD000、length = 0x001000
FLASH_BANK2_SEC14:origin = 0x0AE000、length = 0x001000
FLASH_BANK2_SEC15:origin = 0x0AF000、length = 0x000FF0
// flash_BANK0_SEC15_RSVD:origin = 0x0AFFF0,length = 0x000010 //根据勘误咨询“Memory: prepetching Beyond valid Memory”(内存:超出有效内存的预取),保留代码且不用于代码*/
CLA1_MSGRAMLOW:origin = 0x001480,length = 0x000080
CLA1_MSGRAMHIGH:origin = 0x001500,length = 0x000080
}
部分
{
.cinit:> flash_BANK0_SEC1,align (4)
.text:>> FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC4 | FLASH_BANK0_SEC5| FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7、ALIGN (4)
codestart:>开始,align (4)
.stack:> RAMM1
.switch:> FLASH_BANK0_SEC1,ALIGN (4)
#if defined (_TI_EABI)
init_array:> flash_BANK0_SEC1,align (4)
.bss:> RAMLS5
.bss:输出:> RAMLS5
.bss:CIO :>RAMLS5
.data :> RAMLS6
.sysmem:> RAMLS6
.const:> FLASH_BANK0_SEC4 ALIGN (4)
其他
.pinit:> FLASH_BANK0_SEC1 align (4)
.ebss:>> RAMLS5 | RAMLS6
.esysmem:> RAMLS6
.cio:> RAMLS5
econst:> FLASH_BANK0_SEC4
#endif
RAMS0:> RAMGS0
ramgs1:> RAMGS1
.reset:> reset,type = DSECT /* not used,*/
dclfuncs:> FLASH_BANK0_SEC1、ALIGN (4)
#if defined (_TI_EABI)
/* CLA 特定部分*/
Cla1Prog:load = flash_BANK0_SEC4,
运行= RAMLS0、
Load_start (Cla1ProgLoadStart)、
RUN_START (Cla1ProgRunStart)、
Load_size (Cla1ProgLoadSize)、
对齐(4)
其他
/* CLA 特定部分*/
Cla1Prog:load = flash_BANK0_SEC4,
运行= RAMLS0、
Load_start (_Cla1ProgLoadStart)、
run_start (_Cla1ProgRunStart)、
load_size (_Cla1ProgLoadSize)、
对齐(4)
#endif
Cla1ToCpuMsgRAM:> CLA1_MSGRAMLOW
CpuToCla1MsgRAM:> CLA1_MSGRAMHIGH
IQMath:> FLASH_BANK0_SEC1,ALIGN (8)
IQmathTables:> FLASH_BANK0_sec2,align (8)
#if defined (_TI_EABI)
.TI.ramfunc:load = flash_BANK0_SEC1,
运行= RAMLS4
Load_start (RamfuncsLoadStart)、
load_size (RamfuncsLoadSize)、
Load_End (RamfuncsLoadEnd)、
RUN_START (RamfuncsRunStart)、
run_size (RamfuncsRunSize)、
RUN_END (RamfuncsRunEnd)、
对齐(4)
其他
.TI.ramfunc:load = flash_BANK0_SEC1,
运行= RAMLS4
load_start (_RamfuncsLoadStart)、
load_size (_RamfuncsLoadSize)、
load_end (_RamfuncsLoadEnd)、
run_start (_RamfuncsRunStart)、
run_size (_RamfuncsRunSize)、
run_end (_RamfuncsRunEnd)、
对齐(4)
#endif
暂存区:>RAMLS1
.bss_cla:> RAMLS1
Cla1DataRam:> RAMLS2
CLA_shared:> RAMLS1
CLADataLS1:> RAMLS1
#if defined (_TI_EABI)
const_CLA:load = flash_BANK0_sec2、
运行= RAMLS1、
RUN_START (Cla1ConstRunStart)、
Load_start (Cla1ConstLoadStart)、
load_size (Cla1ConstLoadSize)、
对齐(4)
其他
const_CLA:load = flash_BANK0_sec2、
运行= RAMLS1、
run_start (_Cla1ConstRunStart)、
Load_start (_Cla1ConstLoadStart)、
load_size (_Cla1ConstLoadSize)、
对齐(4)
#endif
}
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////