[参考译文] TMS320F2812：在重复复位之前、时钟输出异常

耶鲁大学

您是说 PLLCR = 0x8时、时钟输出= 30MHz 时存在相同的问题、还是该配置正确获得了120MHz 时钟？

客户使用 TI 函数来更改 SYSCTRL.c 中的 PLL

EALLOW;
      SysCtrlRegs.PLLCR.bit.DIV = val;
      EDIS;

   // Optional: Wait for PLL to lock.
   // During this time the CPU will switch to OSCCLK/2 until the PLL is
   // stable.  Once the PLL is stable the CPU will switch to the new PLL value.
   //
   // This switch time is 131072 CLKIN cycles as of Rev C silicon.
   //
   // Code is not required to sit and wait for the PLL to lock.
   // However, if the code does anything that is timing critical,
   // and requires the correct clock be locked, then it is best to
   // wait until this switching has completed.

   // If this function is run from waitstated memory, then the loop count can
   // be reduced as long as the minimum switch time is still met.

   // iVol is volatile so the compiler will not optimize this loop out
   //
   // The watchdog should be disabled before this loop, or fed within
   // the loop.

      DisableDog();

   // Wait lock cycles.
   // Note,  This loop is tuned to 0-waitstate RAM memory.  If this
   // function is run from wait-stated memory such as Flash or XINTF,
   // then the number of times through the loop can be reduced
   // accordingly.
      for(iVol= 0; iVol< ( (131072/2)/12 ); iVol++)

需要等待一段时间、在此期间需要禁用看门狗、以便它不会复位器件。

如果客户遵循上述要求、则客户系统在一步中从30MHz 变为150MHz 时可能会出现问题。  如果发生上述变化时芯片无法满足其浪涌电流需求、则可能会导致这种情况。  一个潜在的解决方案是以增量步进 PLL、以逐渐增加电流负载、直到释放150MHz。

如果以上都不起作用、我会要求客户在 PLL 变化期间监控 XRSn 引脚、以查看来自器件的任何复位。

最棒的
Matthew