[参考译文] TMS320F280025C：DC 事件、don&#39；t 清除调试窗口中的事件和 don&#39；t 重复频率中断

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请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1170158/tms320f280025c-dc-event-don-t-clear-event-in-debug-window-and-don-t-repeat-tz-interrupt

器件型号：TMS320F280025C

您好！

我的比较器子系统(CMPSS)有问题、我已使用 CMP1_HP2和 CMP1_LP3为 CMPSS1配置一个输入信号、每个比较器具有两个不同的 DAC 阈值。我想在事件发生时触发中断，当我在内部创建断点时，代码停止，所以检测正常，COMPSTS 正常。

稍后、我必须配置另外两个比较器、我想在中断中检测哪个比较器是通过 COMPSTS.bit.COMPHSTS 触发的、哪个比较器是通过另一个比较器的 COMPLSTS 触发的。在中断中、DCBEVT2事件的清零不起作用、中断的 INT 位为什么不起作用？

在不更改比较器输入端的电压电平的同时将断点留在中断中的情况下、我进行两次循环、然后在中断中不再返回任何值、原因是什么？但是、我通过 PieCtrlRegs.PIEACK.bit.ACK2 = 1来确认中断

#include "f28002x_device.h"
#include "HPTS100_tripzone.h"
#include "f28002x_examples.h"

bool test;
__interrupt void tripzone_isr(void)
{
    test = true;
    /// For MU_TRAC_BATT_PCH Comparator subsystem detection, input is triggered CMP1HP2.
    if(Cmpss1Regs.COMPSTS.bit.COMPHSTS == true)
    {
        EALLOW;
        /// Clear the corresponding bit for DCBEVT1 event.
        EPwm1Regs.TZCLR.bit.DCBEVT1 == true;
        EPwm2Regs.TZCLR.bit.DCBEVT1 == true;
        EPwm4Regs.TZCLR.bit.DCBEVT1 == true;
        /// Clear the corresponding bit for DCAEVT1 event.
        EPwm1Regs.TZCLR.bit.DCAEVT1 == true;
        EPwm2Regs.TZCLR.bit.DCAEVT1 == true;
        EPwm4Regs.TZCLR.bit.DCAEVT1 == true;
        /// Clear the corresponding bit for global interrupt.
        EPwm1Regs.TZCLR.bit.INT == true;
        EPwm2Regs.TZCLR.bit.INT == true;
        EPwm4Regs.TZCLR.bit.INT == true;
        EDIS;
    }
    /// For MU_FUEL_CELL_PCH Comparator subsystem detection, input is triggered CMP1_LP3
    if(Cmpss1Regs.COMPSTS.bit.COMPLSTS == true)
    {
        EALLOW;
        /// Clear the corresponding bit for DCBEVT2 event.
        EPwm1Regs.TZCLR.bit.DCBEVT2 == true;
        EPwm2Regs.TZCLR.bit.DCBEVT2 == true;
        EPwm4Regs.TZCLR.bit.DCBEVT2 == true;
        /// Clear the corresponding bit for DCAEVT2 event.
        EPwm1Regs.TZCLR.bit.DCAEVT2 == true;
        EPwm2Regs.TZCLR.bit.DCAEVT2 == true;
        EPwm4Regs.TZCLR.bit.DCAEVT2 == true;
        /// Clear the corresponding bit for global interrupt.
        EPwm1Regs.TZCLR.bit.INT == true;
        EPwm2Regs.TZCLR.bit.INT == true;
        EPwm4Regs.TZCLR.bit.INT == true;
        EDIS;
    }

    /// Acknowledge PIE group 2 to receive more interrupts from this group.
    PieCtrlRegs.PIEACK.bit.ACK2 = 1;
}

void cmpss_init(void)
{
    EALLOW;
    /// Enable CMPSS module.
    Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;
    /// VDDA is the voltage reference for the DAC.
    Cmpss1Regs.COMPDACCTL.bit.SELREF = 0;
    /// DACHVALA so threshold is updated from DACHVALS and not the ramp generator.
    Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 0;
    DELAY_US(1000);

    /// For CMP1_HP2 initialization so MU_TRAC_BATT_PCH
    /// Calculate digital threshold to be passed in DAC register and digital hysteresis.
    THRESHOLD_MU_TRAC_BATT_PCH_DIGITAL = (((THRESHOLD_MU_TRAC_BATT_PCH * 8.2 * 0.00013796) + OFFSET_AMPLI) * ADC_RESOLUTION) / VDDA;
    PARAM_HYST_MU_TRAC_BATT_PCH_DIGITAL = (((PARAM_HYST_MU_TRAC_BATT_PCH * 8.2 * 0.00013796) + OFFSET_AMPLI) * ADC_RESOLUTION) / VDDA;
    /// DAC shadow value.
    Cmpss1Regs.DACHVALS.bit.DACVAL = THRESHOLD_MU_TRAC_BATT_PCH_DIGITAL;
    /// Negative signal come from DAC.
    Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = 0;
    /// Output comparator isn't inverted.
    Cmpss1Regs.COMPCTL.bit.COMPHINV = 0;
    /// Synchronous comparator output drives CTRIPH.
    Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = 1;
    /// Select input mux CMP1HP2 for MU_TRAC_BATT_PCH.
    AnalogSubsysRegs.CMPHPMXSEL.bit.CMP1HPMXSEL = 2;
    /// See ePWM-XBAR architecture for more informations.
    /// For EPWM-XBAR TRIP4 Mux0 select input 0 so CMPSS1.CTRIPH.
    EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0;
    /// Respective output of Mux0 is enabled to drive the TRIP4 of EPWM-XBAR.
    EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;
    DELAY_US(1000);
    /// Trip input 4 selected as combinational Ored input to DCBH mux for EPWMxB.
    EPwm1Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;
    EPwm2Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;
    EPwm4Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;
    /// Trip input 4 selected as combinational Ored input to DCAH mux for EPWMxA.
    EPwm1Regs.DCAHTRIPSEL.bit.TRIPINPUT4 = 1;
    EPwm2Regs.DCAHTRIPSEL.bit.TRIPINPUT4 = 1;
    EPwm4Regs.DCAHTRIPSEL.bit.TRIPINPUT4 = 1;
    /// Select TRIPIN4 for DCTRIPSEL register, digital submodule configuration.
    EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 3;
    EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 3;
    EPwm4Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 3;
    /// Select TRIPIN4 for DCTRIPSEL register, digital submodule configuration.
    EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3;
    EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3;
    EPwm4Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3;
    /// Digital compare output selection, actions when DCBH = high and DCBL don't care. DCBEVT1 event is selected.
    EPwm1Regs.TZDCSEL.bit.DCBEVT1 = 2;
    EPwm2Regs.TZDCSEL.bit.DCBEVT1 = 2;
    EPwm4Regs.TZDCSEL.bit.DCBEVT1 = 2;
    /// Digital compare output selection, actions when DCAH = high and DCAL don't care. DCAEVT1 event is selected.
    EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2;
    EPwm2Regs.TZDCSEL.bit.DCAEVT1 = 2;
    EPwm4Regs.TZDCSEL.bit.DCAEVT1 = 2;
    /// Select DCBEVT1 from source signal.
    EPwm1Regs.DCBCTL.bit.EVT1SRCSEL = 0;
    EPwm2Regs.DCBCTL.bit.EVT1SRCSEL = 0;
    EPwm4Regs.DCBCTL.bit.EVT1SRCSEL = 0;
    /// Select DCAEVT1 from source signal.
    EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 0;
    EPwm2Regs.DCACTL.bit.EVT1SRCSEL = 0;
    EPwm4Regs.DCACTL.bit.EVT1SRCSEL = 0;
    /// Source is synchronized with EPWMCLK for DCBEVT1 event.
    EPwm1Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0;
    EPwm2Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0;
    EPwm4Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0;
    /// Source is synchronized with EPWMCLK for DCAEVT1 event.
    EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0;
    EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0;
    EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0;
    /// Clear the DCBEVT1 trip condition.
    EPwm1Regs.TZCLR.bit.DCBEVT1 = 1;
    EPwm2Regs.TZCLR.bit.DCBEVT1 = 1;
    EPwm4Regs.TZCLR.bit.DCBEVT1 = 1;
    /// Clear the DCAEVT1 trip condition.
    EPwm1Regs.TZCLR.bit.DCAEVT1 = 1;
    EPwm2Regs.TZCLR.bit.DCAEVT1 = 1;
    EPwm4Regs.TZCLR.bit.DCAEVT1 = 1;
    /// Clear the trip interrupt flag for each EPWM modules.
    EPwm1Regs.TZCLR.bit.INT = 1;
    EPwm2Regs.TZCLR.bit.INT = 1;
    EPwm4Regs.TZCLR.bit.INT = 1;
    /// Enable DCBEVT1 interrupt
    EPwm1Regs.TZEINT.bit.DCBEVT1 = 1;
    EPwm2Regs.TZEINT.bit.DCBEVT1 = 1;
    EPwm4Regs.TZEINT.bit.DCBEVT1 = 1;
    /// Enable DCAEVT1 interrupt
    EPwm1Regs.TZEINT.bit.DCAEVT1 = 1;
    EPwm2Regs.TZEINT.bit.DCAEVT1 = 1;
    EPwm4Regs.TZEINT.bit.DCAEVT1 = 1;
    /// Force EPWMxB to a low state when DCBEVT1 event occurs.
    EPwm1Regs.TZCTL.bit.DCBEVT1 = 2;
    EPwm2Regs.TZCTL.bit.DCBEVT1 = 2;
    EPwm4Regs.TZCTL.bit.DCBEVT1 = 2;
    /// Force EPWMxA to a low state when DCAEVT1 event occurs.
    EPwm1Regs.TZCTL.bit.DCAEVT1 = 2;
    EPwm2Regs.TZCTL.bit.DCAEVT1 = 2;
    EPwm4Regs.TZCTL.bit.DCAEVT1 = 2;

    /// For CMP1_LP3 initialization so MU_FUEL_CELL_PCH
    /// Calculate digital threshold to be passed in DAC register and digital hysteresis.
    THRESHOLD_MU_FUEL_CELL_PCH_DIGITAL = (((THRESHOLD_MU_FUEL_CELL_PCH * 8.2 * 0.00013796) + OFFSET_AMPLI) * ADC_RESOLUTION) / VDDA;
    PARAM_HYST_MU_FUEL_CELL_PCH_DIGITAL = (((PARAM_HYST_MU_FUEL_CELL_PCH * 8.2 * 0.00013796) + OFFSET_AMPLI) * ADC_RESOLUTION) / VDDA;
    /// DAC shadow value.
    Cmpss1Regs.DACLVALS.bit.DACVAL = THRESHOLD_MU_FUEL_CELL_PCH_DIGITAL;
    /// Negative signal come from DAC.
    Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = 0;
    /// Output comparator isn't inverted.
    Cmpss1Regs.COMPCTL.bit.COMPHINV = 0;
    /// Synchronous comparator output drives CTRIPL.
    Cmpss1Regs.COMPCTL.bit.CTRIPLSEL = 1;
    /// Select input mux CMP1LP3 for MU_FUEL_CELL_PCH.
    AnalogSubsysRegs.CMPLPMXSEL.bit.CMP1LPMXSEL = 3;
    /// See ePWM-XBAR architecture for more informations.
    /// For EPWM-XBAR TRIP5 Mux1 select input 0 so CMPSS1.CTRIPL.
    EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX1 = 0;
    /// Respective output of Mux1 is enabled to drive the TRIP5 of EPWM-XBAR.
    EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX1 = 1;

    DELAY_US(1000);
    /// Trip input 5 selected as combinational Ored input to DCBL mux for EPWMxB.
    EPwm1Regs.DCBLTRIPSEL.bit.TRIPINPUT5 = 1;
    EPwm2Regs.DCBLTRIPSEL.bit.TRIPINPUT5 = 1;
    EPwm4Regs.DCBLTRIPSEL.bit.TRIPINPUT5 = 1;
    /// Trip input 5 selected as combinational Ored input to DCAL mux for EPWMxA.
    EPwm1Regs.DCALTRIPSEL.bit.TRIPINPUT5 = 1;
    EPwm2Regs.DCALTRIPSEL.bit.TRIPINPUT5 = 1;
    EPwm4Regs.DCALTRIPSEL.bit.TRIPINPUT5 = 1;
    /// Select TRIPIN5 for DCTRIPSEL register, digital submodule configuration.
    EPwm1Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 4;
    EPwm2Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 4;
    EPwm4Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 4;
    /// Select TRIPIN5 for DCTRIPSEL register, digital submodule configuration.
    EPwm1Regs.DCTRIPSEL.bit.DCALCOMPSEL = 4;
    EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = 4;
    EPwm4Regs.DCTRIPSEL.bit.DCALCOMPSEL = 4;
    /// Digital compare output selection, actions when DCBL = high and DCBH = don't care. DCBEVT2 event is select to have the second event for the second comparator and don't erase the first.
    EPwm1Regs.TZDCSEL.bit.DCBEVT2 = 4;
    EPwm2Regs.TZDCSEL.bit.DCBEVT2 = 4;
    EPwm4Regs.TZDCSEL.bit.DCBEVT2 = 4;
    /// Digital compare output selection, actions when DCAH = high and DCAL don't care. DCBEVT2 event is select to have the second event for the second comparator and don't erase the first.
    EPwm1Regs.TZDCSEL.bit.DCAEVT2 = 4;
    EPwm2Regs.TZDCSEL.bit.DCAEVT2 = 4;
    EPwm4Regs.TZDCSEL.bit.DCAEVT2 = 4;
    /// Select DCBEVT2 from source signal.
    EPwm1Regs.DCBCTL.bit.EVT2SRCSEL = 0;
    EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = 0;
    EPwm4Regs.DCBCTL.bit.EVT2SRCSEL = 0;
    /// Select DCAEVT2 from source signal.
    EPwm1Regs.DCACTL.bit.EVT2SRCSEL = 0;
    EPwm2Regs.DCACTL.bit.EVT2SRCSEL = 0;
    EPwm4Regs.DCACTL.bit.EVT2SRCSEL = 0;
    /// Source is synchronized with EPWMCLK for DCBEVT2 event.
    EPwm1Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0;
    EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0;
    EPwm4Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0;
    /// Source is synchronized with EPWMCLK for DCAEVT2 event.
    EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0;
    EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0;
    EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0;
    /// Clear the DCBEVT2 trip condition.
    EPwm1Regs.TZCLR.bit.DCBEVT2 = 1;
    EPwm2Regs.TZCLR.bit.DCBEVT2 = 1;
    EPwm4Regs.TZCLR.bit.DCBEVT2 = 1;
    /// Clear the DCAEVT2 trip condition.
    EPwm1Regs.TZCLR.bit.DCAEVT2 = 1;
    EPwm2Regs.TZCLR.bit.DCAEVT2 = 1;
    EPwm4Regs.TZCLR.bit.DCAEVT2 = 1;
    /// Clear the trip interrupt flag for each EPWM modules.
    EPwm1Regs.TZCLR.bit.INT = 1;
    EPwm2Regs.TZCLR.bit.INT = 1;
    EPwm4Regs.TZCLR.bit.INT = 1;
    /// Enable DCBEVT2 interrupt
    EPwm1Regs.TZEINT.bit.DCBEVT2 = 1;
    EPwm2Regs.TZEINT.bit.DCBEVT2 = 1;
    EPwm4Regs.TZEINT.bit.DCBEVT2 = 1;
    /// Enable DCAEVT2 interrupt
    EPwm1Regs.TZEINT.bit.DCAEVT2 = 1;
    EPwm2Regs.TZEINT.bit.DCAEVT2 = 1;
    EPwm4Regs.TZEINT.bit.DCAEVT2 = 1;
    /// Force EPWMxB to a low state when DCBEVT2 event occurs.
    EPwm1Regs.TZCTL.bit.DCBEVT2 = 2;
    EPwm2Regs.TZCTL.bit.DCBEVT2 = 2;
    EPwm4Regs.TZCTL.bit.DCBEVT2 = 2;
    /// Force EPWMxA to a low state when DCAEVT2 event occurs.
    EPwm1Regs.TZCTL.bit.DCAEVT2 = 2;
    EPwm2Regs.TZCTL.bit.DCAEVT2 = 2;
    EPwm4Regs.TZCTL.bit.DCAEVT2 = 2;

    EDIS;
}

谢谢

Damien

3 年多前

0 admin 3 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Damien：

感谢您的提问、我需要一些时间来测试您的配置并确定问题的根本原因。我将在明天下午返回给你。

－Luke

0 admin 3 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好、Luke、

我等待您的回复。

谢谢

Damien

0 admin 2 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Damien、我仍在处理此问题。同时、您能否发送任何其他相关代码来配置您的 ePWM、例如时基周期、动作限定符等？

0 admin 2 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好、Luke、

我修改了我的代码、将 TZ1集成到触发跳闸区域的 TZ2信号、而不通过数字比较子模块。我正在处理我的问题、结果是我在 ISR 中犯了一个愚蠢的错误。 (例如：EPwm1Regs.TZCLR.bit.DCAEVT2 = true 而不是 EPwm1Regs.TZCLR.bit.DCAEVT2 = true)。

但是、我的问题仍未解决、在我的主 while (1)中留下一个断点、并在我的 ISR 的输入中留下一个断点。如果我使用 F6键在代码中前进(单步执行)、那么我会保持 while (1)、即使我触发了中断、我也不会转到我的中断、如果我执行 F8 (恢复)键、那么我会转到我的中断。

我不使用 F6键转到中断的问题？
另一点是、我在中断中多次循环、因为 PIEACK.ACK2位在中断结束时保持为1。

该位的复位是如何工作的？

知道它不会在我的内部中断条件下停止、因为所有标志都为0、所以中断的循环需要三次。
我希望只执行一个中断循环、而不是执行三个中断循环。我在下图中看到、该位的复位与脉冲的生成一同工作、它是如何工作的？ 3个循环的旋转无论如何都对应于几个周期...

其他问题：如果正确理解 R/W1S 意味着我们可以读取该位并且只写入1、不可以？但“S”是什么意思？

关于中断中不同标志的复位、我希望在激活时看到它们为1、但它们的读数强制为0、不是吗？

谢谢

Damien

0 admin 2 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Damien：

相同的比较器条件是否应该同时触发全部3个 ePWM？我假设这3个中断与您在全部3个 ePWM 上启用的中断相对应。如果您仅在单个 ePWM 上启用此中断、那么您的 ISR 是否仍有3个循环？

此外、在编译器设置中启用优化会导致断点运行异常。您可能还需要测试将其关闭。

0 admin 2 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好、luke、

您可以在没有 ADC 和 GPIO 代码的情况下看到我的代码：

#include "f28002x_device.h"
#include "HPTS100_gpio.h"
#include "HPTS100_epwm.h"
#include "HPTS100_adc.h"
#include "HPTS100_cmpss.h"
#include "HPTS100_tripzone.h"

void InitSysCtrl(void);
void InitPieCtrl(void);
void InitPieVectTable(void);

int main(void)
{
    InitSysCtrl();
    /// Disable CPU interrupts.
    DINT;
    /// Initialize the PIE control registers to their default value.
    InitPieCtrl();
    /// Disable CPU interrupts and clear all cPU interrupt flags.
    IER = 0x0000;
    IFR = 0x0000;
    /// Initialize the PIE vectors table with pointers to the shell Interrupt Service Routine.
    InitPieVectTable();
    /// Authorize register access.
    EALLOW;
    /// Mapping adc_isr function to ADCA_INT interrupt.
    PieVectTable.ADCA1_INT = &adc_isr;
    /// Lock register access.
    EDIS;

    /// Authorize register access.
    EALLOW;
    /// Mapping tripzone_isr function to EPWM1_TZ_INT, EPWM2_TZ_INT, EPWM4_TZ_INT interrupt.
    PieVectTable.EPWM1_TZ_INT = &tripzone_isr;
    PieVectTable.EPWM2_TZ_INT = &tripzone_isr;
    PieVectTable.EPWM4_TZ_INT = &tripzone_isr;
    /// Lock register access.
    EDIS;

    /// Enable group 1 interrupts for ADCA interrupt.
    IER |= M_INT1;
    /// Enable group2 interrupts for trip zone interrupt.
    IER |= M_INT2;
    /// Enable Global interrupt INTM
    EINT;
    /// Enable Global realtime interrupt DBGM
    ERTM;

    /// Enable PIE interrupt 1.1 for ADCA1 interrupt
    PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
    /// Enable PIE interrupt 2.1 for EPWM1 trip zone interrupt
    PieCtrlRegs.PIEIER2.bit.INTx1 = 1;
    /// Enable PIE interrupt 2.2 for EPWM2 trip zone interrupt
    PieCtrlRegs.PIEIER2.bit.INTx2 = 1;
    /// Enable PIE interrupt 2.4 for EPWM4 trip zone interrupt
    PieCtrlRegs.PIEIER2.bit.INTx4 = 1;

    /// GPIO initialization function.
    gpio_init();
    /// EPWM initialization function.
    epwm_init_spwm_u();
    epwm_init_spwm_v();
    epwm_init_spwm_w();
    epwm_init_adc_sync();
    /// Analog to Digital Converter initialization.
    adc_init();
    /// Comparator subsytem initialization.
    cmpss_init();
    /// Configure trip zone for return driver (GPIOmux -> InputXbar -> Trip_zone -> Epwm_module)
    tz_driver_return_init();

    uint16_t cpt = 0;
    while(1)
    {
        cpt++;
        uint16_t test = 0;
    }
}

#include "f28002x_device.h"
#include "HPTS100_tripzone.h"
#include "f28002x_examples.h"

void tz_driver_return_init(void)
{
    EALLOW;
    /// Configure pin for DRV_U_ERROR (TZ1)
    /// Disable the pullup on GPIO45
    GpioCtrlRegs.GPBPUD.bit.GPIO45 = 1;
    /// To define mux position, mux position equal GPBGMUX(2bits) - GPBMUX(2bits) 0 to 15 number.
    GpioCtrlRegs.GPBGMUX1.bit.GPIO45 = 0;
    /// GPIO45 = GPIO45, see pin attributes documentation  for mux position.
    GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 0;
    /// GPIO45 = input
    GpioCtrlRegs.GPBDIR.bit.GPIO45 = 0;
    /// Not inverted GPIO input.
    GpioCtrlRegs.GPBINV.bit.GPIO45 = 0;
    /// Select GPIO45 for TZ1 via INPUT1SELECT
    InputXbarRegs.INPUT1SELECT = 0x2D;
    /// Trip zone submodule mode control logic.
    /// Enable OSHT1 for TZ1 as one shot trip source for each ePWM signals.
    EPwm1Regs.TZSEL.bit.OSHT1 = 1;
    EPwm2Regs.TZSEL.bit.OSHT1 = 1;
    EPwm4Regs.TZSEL.bit.OSHT1 = 1;
    /// Clear the trip set conditions.
    EPwm1Regs.TZCLR.bit.OST = 1;
    EPwm2Regs.TZCLR.bit.OST = 1;
    EPwm4Regs.TZCLR.bit.OST = 1;
    /// Force EPWMxA to a low state when TZA event occurs.
    EPwm1Regs.TZCTL.bit.TZA = 2;
    EPwm2Regs.TZCTL.bit.TZA = 2;
    EPwm4Regs.TZCTL.bit.TZA = 2;
    /// Force EPWMxB to a low state when TZB event occurs.
    EPwm1Regs.TZCTL.bit.TZB = 2;
    EPwm2Regs.TZCTL.bit.TZB = 2;
    EPwm4Regs.TZCTL.bit.TZB = 2;
    /// Trip zone submodule interrupt logic.
    /// Enable one shot interrupt
    EPwm1Regs.TZEINT.bit.OST = 1;
    EPwm2Regs.TZEINT.bit.OST = 1;
    EPwm4Regs.TZEINT.bit.OST = 1;
    /// Clear the trip interrupt flag for each ePWM signals.
    EPwm1Regs.TZCLR.bit.INT = 1;
    EPwm2Regs.TZCLR.bit.INT = 1;
    EPwm4Regs.TZCLR.bit.INT = 1;

    /// Configure pin for DRV_V_ERROR (TZ2)
    /// Disable the pullup on GPIO5
    GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1;
    /// To define mux position, mux position equal GPBGMUX(2bits) - GPBMUX(2bits) 0 to 15 number.
    GpioCtrlRegs.GPAGMUX1.bit.GPIO5 = 0;
    /// GPIO5 = GPIO5, see pin attributes documentation  for mux position.
    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0;
    /// GPIO5 = input
    GpioCtrlRegs.GPADIR.bit.GPIO5 = 0;
    /// Not inverted GPIO input.
    GpioCtrlRegs.GPAINV.bit.GPIO5 = 0;
    /// Select GPIO5 for TZ2 via INPUT2SELECT
    InputXbarRegs.INPUT2SELECT = 0x5;
    /// Trip zone submodule mode control logic.
    /// Enable OSHT2 for TZ2 as one shot trip source for each ePWM signals.
    EPwm1Regs.TZSEL.bit.OSHT2 = 1;
    EPwm2Regs.TZSEL.bit.OSHT2 = 1;
    EPwm4Regs.TZSEL.bit.OSHT2 = 1;
    /// Clear the trip set conditions.
    EPwm1Regs.TZCLR.bit.OST = 1;
    EPwm2Regs.TZCLR.bit.OST = 1;
    EPwm4Regs.TZCLR.bit.OST = 1;
    /// Force EPWMxA to a low state when TZA event occurs.
    EPwm1Regs.TZCTL.bit.TZA = 2;
    EPwm2Regs.TZCTL.bit.TZA = 2;
    EPwm4Regs.TZCTL.bit.TZA = 2;
    /// Force EPWMxB to a low state when TZB event occurs.
    EPwm1Regs.TZCTL.bit.TZB = 2;
    EPwm2Regs.TZCTL.bit.TZB = 2;
    EPwm4Regs.TZCTL.bit.TZB = 2;
    /// Trip zone submodule interrupt logic.
    /// Enable one shot interrupt
    EPwm1Regs.TZEINT.bit.OST = 1;
    EPwm2Regs.TZEINT.bit.OST = 1;
    EPwm4Regs.TZEINT.bit.OST = 1;
    /// Clear the trip interrupt flag for each ePWM signals.
    EPwm1Regs.TZCLR.bit.INT = 1;
    EPwm2Regs.TZCLR.bit.INT = 1;
    EPwm4Regs.TZCLR.bit.INT = 1;


    EDIS;
}

static uint16_t test = 0;
__interrupt void tripzone_isr(void)
{
    test++;
    EALLOW;
    /// For MU_TRAC_BATT_PCH Comparator subsystem detection, input is triggered CMP1HP2.
    if(Cmpss1Regs.COMPSTS.bit.COMPHSTS == true)
    {
        /// Clear the corresponding bit for DCBEVT1 event.
        EPwm1Regs.TZCLR.bit.DCBEVT1 = true;
        EPwm2Regs.TZCLR.bit.DCBEVT1 = true;
        EPwm4Regs.TZCLR.bit.DCBEVT1 = true;
        /// Clear the corresponding bit for DCAEVT1 event.
        EPwm1Regs.TZCLR.bit.DCAEVT1 = true;
        EPwm2Regs.TZCLR.bit.DCAEVT1 = true;
        EPwm4Regs.TZCLR.bit.DCAEVT1 = true;
        /// Clear the corresponding bit for global interrupt.
        EPwm1Regs.TZCLR.bit.INT = true;
        EPwm2Regs.TZCLR.bit.INT = true;
        EPwm4Regs.TZCLR.bit.INT = true;
    }
    /// For MU_FUEL_CELL_PCH Comparator subsystem detection, input is triggered CMP1_LP3
    if(Cmpss1Regs.COMPSTS.bit.COMPLSTS == true)
    {
        /// Clear the corresponding bit for DCBEVT2 event.
        EPwm1Regs.TZCLR.bit.DCBEVT2 = true;
        EPwm2Regs.TZCLR.bit.DCBEVT2 = true;
        EPwm4Regs.TZCLR.bit.DCBEVT2 = true;
        /// Clear the corresponding bit for DCAEVT2 event.
        EPwm1Regs.TZCLR.bit.DCAEVT2 = true;
        EPwm2Regs.TZCLR.bit.DCAEVT2 = true;
        EPwm4Regs.TZCLR.bit.DCAEVT2 = true;
        /// Clear the corresponding bit for global interrupt.
        EPwm1Regs.TZCLR.bit.INT = true;
        EPwm2Regs.TZCLR.bit.INT = true;
        EPwm4Regs.TZCLR.bit.INT = true;
    }
    /// For DRV_U_ERROR
    if(EPwm1Regs.TZOSTFLG.bit.OST1 == true)
    {
        /// Clear the corresponding bit.
        EPwm1Regs.TZOSTCLR.bit.OST1 = true;
        EPwm2Regs.TZOSTCLR.bit.OST1 = true;
        EPwm4Regs.TZOSTCLR.bit.OST1 = true;
        /// Clear the corresponding bit.
        EPwm1Regs.TZCLR.bit.OST = true;
        EPwm2Regs.TZCLR.bit.OST = true;
        EPwm4Regs.TZCLR.bit.OST = true;
        /// Clear the corresponding bit.
        EPwm1Regs.TZCLR.bit.INT = true;
        EPwm2Regs.TZCLR.bit.INT = true;
        EPwm4Regs.TZCLR.bit.INT = true;
    }
    /// For DRV_V_ERROR
    if(EPwm1Regs.TZOSTFLG.bit.OST2 == true)
    {
        /// Clear the corresponding bit.
        EPwm1Regs.TZOSTCLR.bit.OST2 = true;
        EPwm2Regs.TZOSTCLR.bit.OST2 = true;
        EPwm4Regs.TZOSTCLR.bit.OST2 = true;
        /// Clear the corresponding bit.
        EPwm1Regs.TZCLR.bit.OST = true;
        EPwm2Regs.TZCLR.bit.OST = true;
        EPwm4Regs.TZCLR.bit.OST = true;
        /// Clear the corresponding bit.
        EPwm1Regs.TZCLR.bit.INT = true;
        EPwm2Regs.TZCLR.bit.INT = true;
        EPwm4Regs.TZCLR.bit.INT = true;
    }

    EDIS;
    /// Acknowledge PIE group 2 to receive more interrupts from this group.
    PieCtrlRegs.PIEACK.bit.ACK2 = true;
}

我无法重新发布我的 cmpss 配置、但它存在于上一个帖子中。

是的、我配置了三个中断、因为我有3个 PWM、这些中断会穿过触发区、因此我激活相关 PWM 通道的 tz 中断。我想同时激活这三个触发区中断、一个来自触发区比较器的触发信号通过直流模块和 ePWM X 条触发、或者由 GPIO 和触发区直接触发、但在任何情况下、我必须关闭我的3个 PWM。

是否必须配置每个 PWM 的中断才能同时关闭所有 PWM？

我只能触发其中一个、并且仍然关闭3个 PWM、不可以？

谢谢

Damien

0 admin 2 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Damien：

您的中断是否用于关闭您的 ePWM？中断不是必需的、您已经为 ePWM 配置了单次触发、以便在跳闸事件发生时将其驱动至低电平状态。通过在 ISR 中写入 TZCLR.bit.OST、您将清除一次性条件、并允许在跳闸事件发生时重复触发 ISR、从而模仿逐周期跳闸的行为。您的系统中是否有您打算重新激活 ePWM 的事件？发生此事件时、您需要写入 TZCLR.bit.OST。

0 admin 2 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Luke 和其他专家、

现在大家都期待一个关于中断确认的问题：在中断 I aknKnowledge PIE 组的末尾，通过 PieCtrlRegs.PIEACK.bit.ACK2接收更多的中断。

在脉冲生成级别更精确地进行中断确认的方式(图片的步骤4)。在产生该脉冲后，IFR 寄存器是否应设置为0？

这是接收其他中断的条件吗？

谢谢 Damien

0 admin 2 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Vince Toledo 、 Hareesh Janakiraman、

您能否对此图进行说明？

谢谢、

Luke

0 admin 2 年多前

TI__Guru**** 2460140 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Damien：

此处的 TRM 图中更清晰地显示了您提供的图：

[引用 userid="489604" URL"~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1170158/tms320f280025c-dc-event-don-t-clear-event-in-debug-window-and-don-t-repeat-tz-interrupt/4412102 #4412102]中断确认在脉冲生成级别(图中的步骤4)下如何更精确地工作。在生成该脉冲后，IFR 寄存器是否应设置为0？[/QUERPLET]

PIEACK 在图片的步骤4中设置为1 (表示路径"打开")。这可防止在当前 IFR 被处理前更多的 IFR 信号传播到 CPU。

此致、

Vince

C2000™︎ 微控制器（参考译文帖）

C2000™︎ 微控制器（参考译文帖）(Read Only)

[参考译文] TMS320F280025C：DC 事件、don&#39；t 清除调试窗口中的事件和 don&#39；t 重复频率中断