[参考译文] TMS320F280049C：ePWM 示例代码

感谢 Nima 的帮助。 我能够找出我的问题并运行我的代码。 我现在遇到了与 HRPWM 周期控制有关的问题。 我希望它在 HRPWM 模式下运行、这样我就可以对我的周期进行高分辨率控制、并得到 PWM 恰好是155kHz 的频率。 但是、当我将周期设置为数字来实现这一点时、我没有获得准确的信息、也没有获得相应的人力资源控制。 我会在一封单独的邮件中共享我的代码、所以您或许可以帮助我找到我遇到的问题。

感谢您的帮助、Kody

//#############################################################################
//
// FILE:   empty_bitfield_main.c
//
// TITLE:  Empty Example
//
// Empty Bit-Field Example
//
// This example is an empty project setup for Bit-Field development.
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################

//
// Included Files
//
#include "F28x_Project.h"


void InitEpwm1Gpio(void);
void InitEpwm2Gpio(void);
void InitEpwm4Gpio(void);
void InitEpwm5Gpio(void);
void ConfigureEPWM(void);
void InitEpwm1(void);
void InitEpwm2(void);
void InitEpwm4(void);
void InitEpwm5(void);
void InitEpwm1Gpio(void);

Uint16 period = 304;//6.45us/2*10ns for 155kHz
Uint16 dtCountTx = 10; // dead time on both edges
Uint16 dtCountRx = 14;


//
// Main
//
void main(void)
{
    // 1) Initilize System Control
    // PLL, WatchDog, enable Peripheral Clocks
    InitSysCtrl();

    // 2) Initilize GPIOs
    // enable PWM1, PWM2, PWM4, PWM5
    // then init Gpio for same PWMs
    InitGpio(); //May need later if code does not work

    InitEpwm1Gpio();
    InitEpwm2Gpio();
    InitEpwm4Gpio();
    InitEpwm5Gpio();

    // 3) Clear all interrupts and initilize PIE vector table
    // Disaple CPU interrupts
    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();




    // Enable Global Interrupt (INTM) and high priority real-time debug events
    EINT; // Enable INTM
    ERTM; // Enable global realtime interrupt DBGM, may or may not be needed.

    InitEpwm1();
    InitEpwm2();
    InitEpwm4();
    InitEpwm5();
}

//
// ConfigureEPWM - Configure EPWM SOC and compare values confused skip for now
//



//
// EPWM 1 Set up
//
void InitEpwm1(void)
{

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;


    //EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;  // set Shadow load
    EPwm1Regs.TBPRD = period;               // PWM frequency = 1/(2*TBPRD)
    EPwm1Regs.CMPA.bit.CMPA = period / 2;   // set duty 50% initially
    EPwm1Regs.CMPA.bit.CMPAHR = (1 << 8);   // initialize HRPWM extension
    EPwm1Regs.CMPB.bit.CMPB = period / 2;   // set duty 50% initially
    EPwm1Regs.CMPB.all |= 1;
    EPwm1Regs.TBPHS.all = 0;
    EPwm1Regs.TBCTR = 0;

    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down
                                                    // count mode
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT
    EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    //EPwm1Regs.TBCTL.bit.FREE_SOFT = 11;

    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // LOAD CMPA on CTR = 0
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;             // PWM toggle high/low
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;             // PWM toggle high/low
    EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;

    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // set rising and falling edge delay
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm1Regs.DBRED.bit.DBRED = dtCountRx; //rising edge delay
    EPwm1Regs.DBFED.bit.DBFED = dtCountRx; //falling edge delay

    EALLOW;
    EPwm1Regs.HRCNFG.all = 0x0;
    EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP;          // MEP control on
                                                    // both edges.
    EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;          // CMPAHR and TBPRDHR
                                                     // HR control.
    EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;  // load on CTR = 0
                                                     // and CTR = TBPRD
    EPwm1Regs.HRCNFG.bit.EDGMODEB = HR_BEP;         // MEP control on
                                                     // both edges
    EPwm1Regs.HRCNFG.bit.CTLMODEB = HR_CMP;         // CMPBHR and TBPRDHR
                                                     // HR control
    EPwm1Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD; // load on CTR = 0
                                                     // and CTR = TBPRD
    EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;        // Enable autoconversion for
                                               // HR period

    EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1;    // Enable TBPHSHR sync
                                               // (required for updwn
                                               //  count HR control)
    EPwm1Regs.HRPCTL.bit.HRPE = 1;            // Turn on high-resolution
                                               // period control.

    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;      // Enable TBCLK within
                                               // the EPWM
    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
    EPwm1Regs.TBCTL.bit.SWFSYNC = 1;
    EDIS;


}

//
// EPWM 2 Set up
//
void InitEpwm2(void)
{

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;


   // EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;  // set Shadow load
    EPwm2Regs.TBPRD = period;               // PWM frequency = 1/(2*TBPRD)
    EPwm2Regs.CMPA.bit.CMPA = period / 2;   // set duty 50% initially
    EPwm2Regs.CMPA.bit.CMPAHR = (1 << 8);   // initialize HRPWM extension
    EPwm2Regs.CMPB.bit.CMPB = period / 2;   // set duty 50% initially
    EPwm2Regs.CMPB.all |= 1;
    EPwm2Regs.TBPHS.all = 0;
    EPwm2Regs.TBCTR = 0;

    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down
                                                    // count mode
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;          // TBCLK = SYSCLKOUT
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
   // EPwm2Regs.TBCTL.bit.FREE_SOFT = 11;

    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // LOAD CMPA on CTR = 0
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;             // PWM toggle high/low
    EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;             // PWM toggle high/low
    EPwm2Regs.AQCTLB.bit.CBD = AQ_SET;

    EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // set rising and falling edge delay
    EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm2Regs.DBRED.bit.DBRED = dtCountRx; //rising edge delay
    EPwm2Regs.DBFED.bit.DBFED = dtCountRx; //falling edge delay




    EALLOW;
    EPwm2Regs.HRCNFG.all = 0x0;
    EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP;          // MEP control on
                                                    // both edges.
    EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP;          // CMPAHR and TBPRDHR
                                                    // HR control.
    EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;  // load on CTR = 0
                                                     // and CTR = TBPRD
    EPwm2Regs.HRCNFG.bit.EDGMODEB = HR_BEP;         // MEP control on
                                                     // both edges
    EPwm2Regs.HRCNFG.bit.CTLMODEB = HR_CMP;         // CMPBHR and TBPRDHR
                                                     // HR control
    EPwm2Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD; // load on CTR = 0
                                                     // and CTR = TBPRD
    EPwm2Regs.HRCNFG.bit.AUTOCONV = 1;        // Enable autoconversion for
                                               // HR period
    EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1;    // Enable TBPHSHR sync
                                               // (required for updwn
                                               //  count HR control)
    EPwm2Regs.HRPCTL.bit.HRPE = 1;            // Turn on high-resolution
                                               // period control.

    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;      // Enable TBCLK within
                                               // the EPWM
    EPwm2Regs.TBCTL.bit.SWFSYNC = 1;
    EDIS;


}

//
// EPWM 4 Set up
//
void InitEpwm4(void)
{

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;


   // EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;  // set Shadow load
    EPwm4Regs.TBPRD = period;               // PWM frequency = 1/(2*TBPRD)
    EPwm4Regs.CMPA.bit.CMPA = period / 2;   // set duty 50% initially
    EPwm4Regs.CMPA.bit.CMPAHR = (1 << 8);   // initialize HRPWM extension
    EPwm4Regs.CMPB.bit.CMPB = period / 2;   // set duty 50% initially
    EPwm4Regs.CMPB.all |= 1;
    EPwm4Regs.TBPHS.all = 0;
    EPwm4Regs.TBCTR = 0;

    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down
                                                    // count mode
    EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;          // TBCLK = SYSCLKOUT
    EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    EPwm4Regs.TBPHS.bit.TBPHS = period/4;
   // EPwm4Regs.TBCTL.bit.FREE_SOFT = 11;

    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // LOAD CMPA on CTR = 0
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm4Regs.AQCTLA.bit.CAU = AQ_SET;             // PWM toggle high/low
    EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;             // PWM toggle high/low
    EPwm4Regs.AQCTLB.bit.CBD = AQ_SET;

    EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // set rising and falling edge delay
    EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm4Regs.DBRED.bit.DBRED = dtCountTx; //rising edge delay
    EPwm4Regs.DBFED.bit.DBFED = dtCountTx; //falling edge delay

    EALLOW;

    SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN =0;
    EDIS;
    EALLOW;
    EPwm4Regs.HRCNFG.all = 0x0;
    EPwm4Regs.HRCNFG.bit.EDGMODE = HR_BEP;          // MEP control on
                                                    // both edges.
    EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP;          // CMPAHR and TBPRDHR
                                                     // HR control.
    EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;  // load on CTR = 0
                                                     // and CTR = TBPRD
    EPwm4Regs.HRCNFG.bit.EDGMODEB = HR_BEP;         // MEP control on
                                                     // both edges
    EPwm4Regs.HRCNFG.bit.CTLMODEB = HR_CMP;         // CMPBHR and TBPRDHR
                                                     // HR control
    EPwm4Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD; // load on CTR = 0
                                                     // and CTR = TBPRD
    EPwm4Regs.HRCNFG.bit.AUTOCONV = 1;        // Enable autoconversion for
                                               // HR period

    EPwm4Regs.HRPCTL.bit.TBPHSHRLOADE = 1;    // Enable TBPHSHR sync
                                               // (required for updwn
                                               //  count HR control)
    EPwm4Regs.HRPCTL.bit.HRPE = 1;            // Turn on high-resolution
                                               // period control.

    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;      // Enable TBCLK within
                                               // the EPWM
    CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
    EPwm4Regs.TBCTL.bit.SWFSYNC = 1;
    EDIS;


}

//
// EPWM 5 Set up
//
void InitEpwm5(void)
{

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;


    //EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;  // set Shadow load
    EPwm5Regs.TBPRD = period;               // PWM frequency = 1/(2*TBPRD)
    EPwm5Regs.CMPA.bit.CMPA = period / 2;   // set duty 50% initially
    EPwm5Regs.CMPA.bit.CMPAHR = (1 << 8);   // initialize HRPWM extension
    EPwm5Regs.CMPB.bit.CMPB = period / 2;   // set duty 50% initially
    EPwm5Regs.CMPB.all |= 1;
    EPwm5Regs.TBPHS.all = 0;
    EPwm5Regs.TBCTR = 0;

    EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down
                                                    // count mode
    EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;          // TBCLK = SYSCLKOUT
    EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    //EPwm5Regs.TBPHS.bit.TBPHS = period/4;
    //EPwm5Regs.TBCTL.bit.FREE_SOFT = 11;

    EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // LOAD CMPA on CTR = 0
    EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;             // PWM toggle high/low
    EPwm5Regs.AQCTLA.bit.CAD = AQ_SET;
    EPwm5Regs.AQCTLB.bit.CBU = AQ_SET;             // PWM toggle high/low
    EPwm5Regs.AQCTLB.bit.CBD = AQ_CLEAR;

    EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // set rising and falling edge delay
    EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm5Regs.DBRED.bit.DBRED = dtCountTx; //rising edge delay
    EPwm5Regs.DBFED.bit.DBFED = dtCountTx; //falling edge delay


    EALLOW;
    EPwm5Regs.HRCNFG.all = 0x0;
    EPwm5Regs.HRCNFG.bit.EDGMODE = HR_BEP;          // MEP control on
                                                   // both edges.
    EPwm5Regs.HRCNFG.bit.CTLMODE = HR_CMP;          // CMPAHR and TBPRDHR
                                                     // HR control.
    EPwm5Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;  // load on CTR = 0
                                                     // and CTR = TBPRD
    EPwm5Regs.HRCNFG.bit.EDGMODEB = HR_BEP;         // MEP control on
                                                     // both edges
    EPwm5Regs.HRCNFG.bit.CTLMODEB = HR_CMP;         // CMPBHR and TBPRDHR
                                                    // HR control
    EPwm5Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD; // load on CTR = 0
                                                     // and CTR = TBPRD
    EPwm5Regs.HRCNFG.bit.AUTOCONV = 1;        // Enable autoconversion for
                                               // HR period
    EPwm5Regs.HRPCTL.bit.TBPHSHRLOADE = 1;    // Enable TBPHSHR sync
                                               // (required for updwn
                                               //  count HR control)
    EPwm5Regs.HRPCTL.bit.HRPE = 1;            // Turn on high-resolution
                                               // period control.

    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;  // Enable TBCLK within
                                               // the EPWM

    EPwm5Regs.TBCTL.bit.SWFSYNC = 1;
    EDIS;


}





//
// End of File
//

"对不起,我不小心给弄丢了。" 您还有问题吗？或者问题是否已解决？

不用担心 Nima、我还没有想出我的 HR PWM 控制的问题。 即使设置的周期数正确、高分辨率周期控制也不能正常工作。  

不用担心 Nima、我还没有想出我的 HR PWM 控制的问题。 即使设置的周期数正确、高分辨率周期控制也不能正常工作。