[参考译文] TMS320F280041C：基于其他 ePWM 开启和关闭事件控制 ePWM 输出

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Other Parts Discussed in Thread: TMS320F280041, C2000WARE

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1249896/tms320f280041c-control-epwm-outputs-based-on-other-epwm-on-and-off-events

器件型号：TMS320F280041
主题中讨论的其他器件： C2000WARE

您好！

我正在使用 TMS320F280041微控制器实现对相移全桥转换器的控制。
电源通过 EPWM1-EPWM4相移进行控制。 EPWM1和 EPWM4设置为向上向下模式并链接(EPWM1同步输出用作 EPWM4同步输入、并通过 TBPHS 寄存器进行相位控制)。频率为100kHz、占空比为50%。相移在范围(1；0、5)内(epwm1滞后于 epwm4)。控制环路频率为10kHz

这对我来说很好。

但是、我将尝试使用 EPWM1和 EPM4输出关闭和开启事件在 EPM7上实现同步整流器控制、与本主题中所述的类似：

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1158329/tms320f280048-q1-how-to-obtain-sr-waveforms-by-monitoring-other-epwm-channels-on-and-off-edges?tisearch=e2e-sitesearch&keymatch=synchronize%252520rectifier#

我使用 T1事件来实现该目的、其理念是：

EPWM1：向上向下计数模式、在 CMPA 向上计数时开启、在 CMPA 向下计数时关闭

EPWM4：上升/下降模式、在 CMPA 上升时开启、关闭 CMPA 下降、相对于 EPWM1的相移、CMPB 等于 CMPA 对于 EPWM7是同步输出

EPWM7：向上/向下模式、默认设置为 EPWM1、但从 EPWM4同步输入用作 T1事件、因此输出由 T1和 CMPA 事件控制

正如我看到的、T1的逻辑与相移有关。当相移大于0.75时、我用于控制 EPWM7输出的事件为 T1D、低于0.75、此事件将更改为 T1U。
因此、我必须为 EPWM7更改动作限定器的"动态"配置。

问题是、当我在相移为0.75时更改此配置(我是通过检查 TBPRD 和 TBPHS 寄存器及其关系来进行此操作)、那么有时候看起来好像太早了-
动作限定器配置已更改、因此它会对 T1U 而不是 T1D 做出反应、这会破坏所需的 PWM 波形。

您能帮助我调查并理解这个问题吗？如果需要、我稍后会用代码和图像更新此主题。

我想继续使用 T1事件方法、因为我正在使用带有 CMPSS 的数字比较模块进行保护

9 个月前

0 admin 9 个月前

TI__Guru**** 666710 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Dawid：

您能否澄清一下这句话：

"对于 EPWM7、CMPB 等于 CMPA 是同步输出"

没有配置可在 CMPA=CMPB 上生成同步输出脉冲。这是您的意思吗？

EPWM7是否与 EPWM1同步？ EPWM7的同步输入源是什么？

谢谢！

卢克

0 admin 9 个月前

TI__Guru**** 666710 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

这是一个复杂的配置。如果您还可以发送所看到波形的示波器快照、所需波形的图或描述、并列出在运行期间更改的有助于解决此问题的所有设置。

0 admin 9 个月前

TI__Guru**** 666710 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Luke、您好！

很抱歉回复晚了、我在发布任何内容时遇到问题。

"CMPB 等于 CMPA 是 EPWM7的同步输出"意味着 EPWM4的 CMPB 具有与 EPWM4的 CMPA 相同的值、并且 CMPB 是 EPWM7的同步输出源。

以下是相关设置的代码配置。实际上、已设计的配置有一点改变：我需要在同步整流器上实现一些延迟、因此是通过 EPWM7A 和 EPWM8A 输出上的上升沿死区时间完成的。

下面是我要实现的波形-模式2的示例

下面是我对波形的情况：

以上相移超过0.75、因此我将根据我的初始配置、即 EPWM7和 EPWM8的动作限定符来切换 SR。

但这里有一个问题：

EPWM4的下降沿将成为我的 T1向上事件、然后我才能切换动作限定符的配置。

我尝试了许多寄存器隐藏或同步配置、但我不明白为什么会发生这种情况。

有什么想法吗？

此致
达维德

/* EPWM1 setting (master): */

    EPwm1Regs.TBCTL.bit.CLKDIV = 0;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
	EPwm1Regs.TBPHS.bit.TBPHS = 0; // set Phase register to zero
	EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // symmetrical mode
	EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // master module
	EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and Prd
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and Prd
    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    EPwm1Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
    EPwm1Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
	EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
	EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // active Hi complementary
	EPwm1Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;
	EPwm1Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;
	EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;

    EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;
    EPwm1Regs.ETSEL.bit.SOCAEN = 0;
    EPwm1Regs.ETSOCPS.bit.SOCAPRD2 = 1;
	
	  EPwm1Regs.outMode = PLX_PWM_OUTPUT_MODE_DUAL;
      EPwm1Regs.TBPRD = 500;
      EPwm1Regs.TBCTL.bit.CTRMODE = 2;
      // activestate is high
      EPwm1Regs.DBCTL.bit.POLSEL = 2; // DB_ACTV_HIC
      // enable deadtime insertion
      EPwm1Regs.DBCTL.bit.OUT_MODE = 3; // DB_FULL_ENABLE
      EPwm1Regs.DBCTL.bit.IN_MODE = 0; // DBA_ALL
      // TZ settings
      EPwm1Regs.TZSEL.bit.CBC1 = 0;
      EPwm1Regs.TZSEL.bit.OSHT1 = 0;
      EPwm1Regs.TZSEL.bit.CBC2 = 0;
      EPwm1Regs.TZSEL.bit.OSHT2 = 0;
      EPwm1Regs.TZSEL.bit.CBC3 = 0;
      EPwm1Regs.TZSEL.bit.OSHT3 = 0;
      // force low when tripped
      EPwm1Regs.TZCTL.bit.TZA = 2;
      EPwm1Regs.TZCTL.bit.TZB = 2;
	 
    // shadowing to allow synchronized disabling of leg
    EPwm1Regs.DBCTL2.bit.SHDWDBCTLMODE = 1; // shadow [5:0]of the DBCTL
    EPwm1Regs.DBCTL2.bit.LOADDBCTLMODE = 0; // load at zero
    EPwm1Regs.AQSFRC.bit.RLDCSF = 0; // load software force on zero
	EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;
	

/* EPWM4 setting (slave): */

    EPwm4Regs.TBCTL.bit.CLKDIV = 0;
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0;
	EPwm4Regs.TBPHS.bit.TBPHS = 0; // set Phase register to zero
	EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // symmetrical mode
	EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // master module
	EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and Prd
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and Prd
    EPwm4Regs.AQCTLA.bit.CAU = AQ_SET;
    EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    EPwm4Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
    EPwm4Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
	EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
	EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // active Hi complementary
	EPwm4Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;
	EPwm4Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;
	EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;

    EPwm4Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;
    EPwm4Regs.ETSEL.bit.SOCAEN = 0;
    EPwm4Regs.ETSOCPS.bit.SOCAPRD2 = 1;
	
	  EPwm4Regs.outMode = PLX_PWM_OUTPUT_MODE_DUAL;
      EPwm4Regs.TBPRD = 500;
      EPwm4Regs.TBCTL.bit.CTRMODE = 2;
      // activestate is high
      EPwm4Regs.DBCTL.bit.POLSEL = 2; // DB_ACTV_HIC
      // enable deadtime insertion
      EPwm4Regs.DBCTL.bit.OUT_MODE = 3; // DB_FULL_ENABLE
      EPwm4Regs.DBCTL.bit.IN_MODE = 0; // DBA_ALL
      // TZ settings
      EPwm4Regs.TZSEL.bit.CBC1 = 0;
      EPwm4Regs.TZSEL.bit.OSHT1 = 0;
      EPwm4Regs.TZSEL.bit.CBC2 = 0;
      EPwm4Regs.TZSEL.bit.OSHT2 = 0;
      EPwm4Regs.TZSEL.bit.CBC3 = 0;
      EPwm4Regs.TZSEL.bit.OSHT3 = 0;
      // force low when tripped
      EPwm4Regs.TZCTL.bit.TZA = 2;
      EPwm4Regs.TZCTL.bit.TZB = 2;
	 
    // shadowing to allow synchronized disabling of leg
    EPwm4Regs.DBCTL2.bit.SHDWDBCTLMODE = 1; // shadow [5:0]of the DBCTL
    EPwm4Regs.DBCTL2.bit.LOADDBCTLMODE = 0; // load at zero
    EPwm4Regs.AQSFRC.bit.RLDCSF = 0; // load software force on zero
	EPwm4Regs.TBCTL.bit.SYNCOSEL = 0;
	EPwm4Regs.TBCTL2.bit.PRDLDSYNC = 1;       // load TBPRD at zero and SYNC
    EALLOW;
    SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = 0;
    EDIS;
	
/* EPWM7 default configuration(SR A on EPWM7A ) */	
	
	EPwm7Regs.TBCTL.bit.CLKDIV = 0;
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0;
	EPwm7Regs.TBPHS.bit.TBPHS = 0; // set Phase register to zero
	EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // symmetrical mode
	EPwm7Regs.TBCTL.bit.PHSEN = TB_DISABLE; // master module
	EPwm7Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and Prd
    EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and Prd
    EPwm7Regs.AQCTLA.bit.CAU = AQ_SET;
    EPwm7Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    EPwm7Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
    EPwm7Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
	EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
	EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // active Hi complementary
	EPwm7Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;
	EPwm7Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;
	EPwm7Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;

    EPwm7Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;
    EPwm7Regs.ETSEL.bit.SOCAEN = 0;
    EPwm7Regs.ETSOCPS.bit.SOCAPRD2 = 1;
	
	  EPwm7Regs.outMode = PLX_PWM_OUTPUT_MODE_DUAL;
      EPwm7Regs.TBPRD = 500;
      EPwm7Regs.TBCTL.bit.CTRMODE = 2;
      // activestate is high
      EPwm7Regs.DBCTL.bit.POLSEL = 2; // DB_ACTV_HIC
      // enable deadtime insertion
      EPwm7Regs.DBCTL.bit.OUT_MODE = 3; // DB_FULL_ENABLE
      EPwm7Regs.DBCTL.bit.IN_MODE = 0; // DBA_ALL
      // TZ settings
      EPwm7Regs.TZSEL.bit.CBC1 = 0;
      EPwm7Regs.TZSEL.bit.OSHT1 = 0;
      EPwm7Regs.TZSEL.bit.CBC2 = 0;
      EPwm7Regs.TZSEL.bit.OSHT2 = 0;
      EPwm7Regs.TZSEL.bit.CBC3 = 0;
      EPwm7Regs.TZSEL.bit.OSHT3 = 0;
      // force low when tripped
      EPwm7Regs.TZCTL.bit.TZA = 2;
      EPwm7Regs.TZCTL.bit.TZB = 2;
	 
    // shadowing to allow synchronized disabling of leg
    EPwm7Regs.DBCTL2.bit.SHDWDBCTLMODE = 1; // shadow [5:0]of the DBCTL
    EPwm7Regs.DBCTL2.bit.LOADDBCTLMODE = 0; // load at zero
    EPwm7Regs.AQSFRC.bit.RLDCSF = 0; // load software force on zero
	EPwm7Regs.TBCTL.bit.SYNCOSEL = 1;

/* EPWM8 default configuration(SR B on EPWM8A ) */

    EPwm8Regs.TBCTL.bit.CLKDIV = 0;
    EPwm8Regs.TBCTL.bit.HSPCLKDIV = 0;		
	EPwm8Regs.TBPHS.bit.TBPHS = 0; // set Phase register to zero
	EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // symmetrical mode
	EPwm8Regs.TBCTL.bit.PHSEN = TB_DISABLE; // master module
	EPwm8Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and Prd
    EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and Prd
    EPwm8Regs.AQCTLA.bit.CAU = AQ_SET;
    EPwm8Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    EPwm8Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
    EPwm8Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
	EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
	EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // active Hi complementary
	EPwm8Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;
	EPwm8Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;
	EPwm8Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;

    EPwm8Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;
    EPwm8Regs.ETSEL.bit.SOCAEN = 0;
    EPwm8Regs.ETSOCPS.bit.SOCAPRD2 = 1;
	
	  EPwm8Regs.outMode = PLX_PWM_OUTPUT_MODE_DUAL;
      EPwm8Regs.TBPRD = 500;
      EPwm8Regs.TBCTL.bit.CTRMODE = 2;
      // activestate is high
      EPwm8Regs.DBCTL.bit.POLSEL = 2; // DB_ACTV_HIC
      // enable deadtime insertion
      EPwm8Regs.DBCTL.bit.OUT_MODE = 3; // DB_FULL_ENABLE
      EPwm8Regs.DBCTL.bit.IN_MODE = 0; // DBA_ALL
      // TZ settings
      EPwm8Regs.TZSEL.bit.CBC1 = 0;
      EPwm8Regs.TZSEL.bit.OSHT1 = 0;
      EPwm8Regs.TZSEL.bit.CBC2 = 0;
      EPwm8Regs.TZSEL.bit.OSHT2 = 0;
      EPwm8Regs.TZSEL.bit.CBC3 = 0;
      EPwm8Regs.TZSEL.bit.OSHT3 = 0;
      // force low when tripped
      EPwm8Regs.TZCTL.bit.TZA = 2;
      EPwm8Regs.TZCTL.bit.TZB = 2;
	 
    // shadowing to allow synchronized disabling of leg
    EPwm8Regs.DBCTL2.bit.SHDWDBCTLMODE = 1; // shadow [5:0]of the DBCTL
    EPwm8Regs.DBCTL2.bit.LOADDBCTLMODE = 0; // load at zero
    EPwm8Regs.AQSFRC.bit.RLDCSF = 0; // load software force on zero
	EPwm8Regs.TBCTL.bit.SYNCOSEL = 1;



/* Configuring controlling SR with EPWM1 and EPWM4 events
    it overwrites some previous settings */

   EALLOW;

   EPwm7Regs.TBPHS.all = 0x0u;
   /*************************************************************/
   /* setting for solution on one  epwms - config for EPWM7*/
   EPwm7Regs.DBCTL.all = 0u; //disable deadband
   EPwm7Regs.DBCTL.bit.OUT_MODE = 2; //2 - (Rising Edge Delay in A signal path), 3 - DBM fully active

   EPwm4Regs.CMPB.bit.CMPB = EPwm4Regs.CMPA.bit.CMPA;
   EPwm4Regs.TBCTL.bit.SYNCOSEL = 2; //syncosel on CMPB
   SyncSocRegs.SYNCSELECT.bit.EPWM7SYNCIN = 1; //EPWM4SYNCOUT selected

   EPwm7Regs.AQTSRCSEL.bit.T1SEL = 7; //EPWMxSYNCI

   EPwm8Regs.DBCTL.all = 0u; //disable deadband
   EPwm8Regs.DBCTL.bit.OUT_MODE = 2; //2 - (Rising Edge Delay in A signal path), 3 - DBM fully

   EPwm7Regs.TBCTL.bit.SYNCOSEL = 0; //syncosel on CMPB of EPWM4 (EPWM 7 SYNCIN)

   EPwm8Regs.AQTSRCSEL.bit.T1SEL = 7; //EPWMxSYNCI

   //  /* AQCTL setting - shadow registers */
   EPwm7Regs.AQCTL.bit.SHDWAQAMODE = 1; //turn on shadow mode for AQCTLA
   EPwm7Regs.AQCTL.bit.SHDWAQBMODE = 1; //turn on shadow mode for AQCTLB
   EPwm8Regs.AQCTL.bit.SHDWAQAMODE = 1; //turn on shadow mode for AQCTLA
   EPwm8Regs.AQCTL.bit.SHDWAQBMODE = 1; //turn on shadow mode for AQCTLB
   //
   EPwm7Regs.AQCTL.bit.LDAQAMODE = 1; //2-shadow Load on CTR = Zero or CTR = PRD, 0 - on zero
   EPwm7Regs.AQCTL.bit.LDAQBMODE = 1; //2-shadow Load on CTR = Zero or CTR = PRD, 0 - on zero
   EPwm8Regs.AQCTL.bit.LDAQAMODE = 1; //2-shadow Load on CTR = Zero or CTR = PRD, 1 - on period
   EPwm8Regs.AQCTL.bit.LDAQBMODE = 1; //2-shadow Load on CTR = Zero or CTR = PRD, 1 - on period
   //
   /* when solo EPwmxRegs.AQCTL.bit.LDAQxSYNC = 1; then always logic for A and B is correct */
   EPwm7Regs.AQCTL.bit.LDAQASYNC = 1; // 0- Shadow to Active Load of AQCTLB occurs according to LDAQAMODE, 1 - on ldaqamode and sync
   EPwm7Regs.AQCTL.bit.LDAQBSYNC = 1; //Shadow to Active Load of AQCTLB occurs according to LDAQAMODE, 1 - on ldaqamode and sync
   EPwm8Regs.AQCTL.bit.LDAQASYNC = 1; //Shadow to Active Load of AQCTLB occurs according to LDAQAMODE, 1 - on ldaqamode and sync
   EPwm8Regs.AQCTL.bit.LDAQBSYNC = 1; //Shadow to Active Load of AQCTLB occurs according to LDAQAMODE, 1 - on ldaqamode and sync, 2 - only on sync

   /* Start with SR disabled */
   SynchrRectOnEventsTurnOff();
   
   EDIS;
   
   
   
/* Controlling phase shift for EPWM4 - except this there is also usage of HRPWM */

void EPWM4_setPhase( float aPhase)
{
    if((aPhase < 0) || (aPhase >= 1.0))
    {
        aPhase = 0;
    }

    uint16_t phase;
    uint16_t dir;
    if(EPwm4Regs.TBCTL.bit.CTRMODE == TB_COUNT_UPDOWN)
    {
        // up-down
        if (aPhase <= 0.5)
        {
            // -2 to compensate 2*EPWMCLK delay to synchronize EPWM_master and EPWM_slave
            phase = (uint16_t)((float)(EPwm4Regs.TBPRD) * aPhase) -2;
            dir = 0;
        }
        else
        {
            // +2 to compensate 2*EPWMCLK delay to synchronize EPWM_master and EPWM_slave, +1 to compensate dir
            phase = (uint16_t)((float)(EPwm4Regs.TBPRD) * (1-aPhase)) + 3;
            dir = 1;
        }
    }
    else
    {
        // saw-tooth
        // +2 co compensate EPWM clk delay, +1 to compensate dir
        phase = (uint16_t)(((float)EPwm4Regs.TBPRD+1) * (1-aPhase)) + 3;
        if(phase > EPwm4Regs.TBPRD)
        {
            phase = 0;
        }
        dir = 0;
    }
    EPwm4Regs.TBPHS.bit.TBPHS= phase;
    EPwm4Regs.TBCTL.bit.PHSDIR = dir;
}

/******** Controling SR functions ************/

static void SynchrRectOnEventsTurnOff(void)
{
   //when modes disabled, then set outputs low
   //SR A (EPWM 7A)
   EPwm7Regs.AQCTLA2.bit.T1D = AQ_CLEAR;
   EPwm7Regs.AQCTLA2.bit.T1U = AQ_CLEAR;
   EPwm7Regs.AQCTLA.bit.CAD = AQ_CLEAR;
   EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR;
   EPwm7Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
   EPwm7Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
   //SR B (EPWM 7B)
   EPwm7Regs.AQCTLB2.bit.T1U = AQ_CLEAR;
   EPwm7Regs.AQCTLB.bit.CAU = AQ_CLEAR;
   EPwm7Regs.AQCTLB2.bit.T1D = AQ_CLEAR;
   EPwm7Regs.AQCTLB.bit.CAD = AQ_CLEAR;
   EPwm7Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
   EPwm7Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;
   //SR B (EPWM 8A)
   EPwm8Regs.AQCTLA2.bit.T1U = AQ_CLEAR;
   EPwm8Regs.AQCTLA.bit.CAU = AQ_CLEAR;
   EPwm8Regs.AQCTLA2.bit.T1D = AQ_CLEAR;
   EPwm8Regs.AQCTLA.bit.CAD = AQ_CLEAR;
   EPwm8Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
   EPwm8Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
}

static void SynchrRectOnEventsConfig(uint16_t srMode,
                                                  uint16_t shift)
{
   /* srMode provided with SR Modulator logic */
   switch(srMode)
   {
   case 1u:
      /* when SR for low currents */
      /* when shift below threshold */
      if(shift == 1u)
      {
         EPwm7Regs.AQCTLA2.bit.T1U = AQ_SET;
         EPwm7Regs.AQCTLA2.bit.T1D = AQ_NO_ACTION;
         EPwm7Regs.AQCTLB2.bit.T1D = AQ_SET;
         EPwm7Regs.AQCTLB2.bit.T1U = AQ_NO_ACTION;
         EPwm8Regs.AQCTLA2.bit.T1D = AQ_SET;
         EPwm8Regs.AQCTLA2.bit.T1U = AQ_NO_ACTION;
         EPwm7Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;

      }
      else
      {
         EPwm7Regs.AQCTLA2.bit.T1D = AQ_SET;
         EPwm7Regs.AQCTLA2.bit.T1U = AQ_NO_ACTION;
         EPwm7Regs.AQCTLB2.bit.T1D = AQ_NO_ACTION;
         EPwm7Regs.AQCTLB2.bit.T1U = AQ_SET;
         EPwm8Regs.AQCTLA2.bit.T1U = AQ_SET;
         EPwm8Regs.AQCTLA2.bit.T1D = AQ_NO_ACTION;
         //to deal with wrong pwm for 1 epwmclk
         EPwm7Regs.AQCTLA.bit.PRD = AQ_CLEAR;
      }
      /* independent actions from phase shift */
      EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR;
      EPwm7Regs.AQCTLA.bit.CAD = AQ_NO_ACTION;
      EPwm7Regs.AQCTLB.bit.CAD = AQ_CLEAR;
      EPwm7Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
      EPwm8Regs.AQCTLA.bit.CAD = AQ_CLEAR;
      EPwm8Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
      break;

   case 2u:
      /* when SR for high currents */
      /* when shift below threshold */
      if(shift == 1u)
      {
         EPwm7Regs.AQCTLA2.bit.T1D = AQ_CLEAR;
         EPwm7Regs.AQCTLA2.bit.T1U = AQ_NO_ACTION;
         EPwm7Regs.AQCTLB2.bit.T1U = AQ_CLEAR;
         EPwm7Regs.AQCTLB2.bit.T1D = AQ_NO_ACTION;
         EPwm8Regs.AQCTLA2.bit.T1U = AQ_CLEAR;
         EPwm8Regs.AQCTLA2.bit.T1D = AQ_NO_ACTION;
         // EPwm7Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;

      else
      {
         EPwm7Regs.AQCTLA2.bit.T1D = AQ_NO_ACTION;
         EPwm7Regs.AQCTLA2.bit.T1U = AQ_CLEAR;
         EPwm7Regs.AQCTLB2.bit.T1D = AQ_CLEAR;
         EPwm7Regs.AQCTLB2.bit.T1U = AQ_NO_ACTION;
         EPwm8Regs.AQCTLA2.bit.T1U = AQ_NO_ACTION;
         EPwm8Regs.AQCTLA2.bit.T1D = AQ_CLEAR;



      }
      /* independent actions from phase shift */
      EPwm7Regs.AQCTLA.bit.CAD = AQ_SET;
      EPwm7Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
      EPwm7Regs.AQCTLB.bit.CAU = AQ_SET;
      EPwm7Regs.AQCTLB.bit.CAD = AQ_NO_ACTION;
      EPwm8Regs.AQCTLA.bit.CAU = AQ_SET;
      EPwm8Regs.AQCTLA.bit.CAD = AQ_NO_ACTION;
      break;

   default:
      /*SR disabled */
      SynchrRectOnEventsTurnOff();
      break;
   }
}

void ControlSR(uint16_t srMode, bool bursMode)
{
   EALLOW;

   uint16_t phaseVal = EPwm4Regs.TBPHS.bit.TBPHS;

   /* to control synchronous rectifier */
   EPwm7Regs.CMPA.bit.CMPA = (uint16_t)((float)EPwm7Regs.TBPRD * 0.5f);
   EPwm8Regs.CMPA.bit.CMPA = (uint16_t)((float)EPwm8Regs.TBPRD * 0.5f);
   EPwm7Regs.TBPHS.all = 0x0u;
   EPwm8Regs.TBPHS.all = 0x0u;

   EPwm4Regs.CMPB.bit.CMPB = EPwm4Regs.CMPA.bit.CMPA;

   uint16_t phaseThrshld = (uint16_t)((float)EPwm4Regs.TBPRD * 0.5f) + 3u;
   if(phaseVal < phaseThrshld)
   {
      SynchrRectOnEventsConfig(srMode, 1u);
   }
   else
   {
      SynchrRectOnEventsConfig(srMode, 2u);
   }
   /* when burst mode active (frequency of legs is 50 kHz)*/
   if( bursMode == true )
   {
      /* disable SR when burst mode active */
      SynchrRectOnEventsTurnOff();
   }
   EDIS;

   /******** END OF NATIVE CODE step : SR on events config ******/
}

0 admin 9 个月前

TI__Guru**** 666710 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Dawid：

是否尝试过使用全局加载？这将确保在 ePWM TBCTR = 0时加载 EPWM7的更新操作限定器设置和 EPWM4的新相移。

另一个可能更容易实现的选项是使用 CLB 生成所需的 EPWM7输出。您可以在 CLB 中使用 FSM、在 EPWM1的任何上升沿触发 EPWM7输出的上升沿、并在 EPWM4的任何上升沿触发 EPWM7输出的下降沿。这可能比动态更改 EPWM7的动作限定器设置更可靠。

谢谢！

卢克

0 admin 9 个月前

TI__Guru**** 666710 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好

我曾尝试设置全局加载、但没有帮助。以下是我的配置：

/* global load setting */
// Sync source ePWM1 settings
EPWM_enableGlobalLoadRegisters(EPWM1_BASE, EPWM_GL_REGISTER_CMPA_CMPAHR|EPWM_GL_REGISTER_CMPB_CMPBHR|
 EPWM_GL_REGISTER_AQCTLA_AQCTLA2);
EPWM_setGlobalLoadTrigger(EPWM1_BASE, EPWM_GL_LOAD_PULSE_CNTR_PERIOD);
EPWM_enableGlobalLoadOneShotMode(EPWM1_BASE);
EPWM_enableGlobalLoad(EPWM1_BASE);

// Sync receiver ePWM4 settings
EPWM_enableGlobalLoadRegisters(EPWM4_BASE, EPWM_GL_REGISTER_CMPA_CMPAHR|EPWM_GL_REGISTER_CMPB_CMPBHR|
 EPWM_GL_REGISTER_AQCTLA_AQCTLA2);
EPWM_setGlobalLoadTrigger(EPWM4_BASE, EPWM_GL_LOAD_PULSE_SYNC);
EPWM_enableGlobalLoadOneShotMode(EPWM4_BASE);
EPWM_enableGlobalLoad(EPWM4_BASE);
EPWM_setupEPWMLinks(EPWM4_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_GLDCTL2);

// Sync receiver ePWM7 settings
EPWM_enableGlobalLoadRegisters(EPWM7_BASE, EPWM_GL_REGISTER_CMPA_CMPAHR|EPWM_GL_REGISTER_CMPB_CMPBHR|
 EPWM_GL_REGISTER_AQCTLA_AQCTLA2);
EPWM_setGlobalLoadTrigger(EPWM7_BASE, EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO);
EPWM_enableGlobalLoadOneShotMode(EPWM7_BASE);
EPWM_enableGlobalLoad(EPWM7_BASE);
EPWM_setupEPWMLinks(EPWM7_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_GLDCTL2);

// Sync receiver ePWM8 settings
EPWM_enableGlobalLoadRegisters(EPWM8_BASE, EPWM_GL_REGISTER_CMPA_CMPAHR|EPWM_GL_REGISTER_CMPB_CMPBHR|
 EPWM_GL_REGISTER_AQCTLA_AQCTLA2);
EPWM_setGlobalLoadTrigger(EPWM8_BASE, EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO);
EPWM_enableGlobalLoadOneShotMode(EPWM8_BASE);
EPWM_enableGlobalLoad(EPWM8_BASE);
EPWM_setupEPWMLinks(EPWM8_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_GLDCTL2);



/* During controling sr */
EPWM_setGlobalLoadOneShotLatch(EPWM1_BASE);
EPWM_setGlobalLoadOneShotLatch(EPWM4_BASE);
EPWM_setGlobalLoadOneShotLatch(EPWM7_BASE);
EPWM_setGlobalLoadOneShotLatch(EPWM8_BASE);

我没有考虑使用 CLB。是否可以像使用死区时间发生器一样使用 CLB 引入一定的延迟？您能举几个例子来说明一下、如果我想尝试一下、哪些示例会很有用吗？

此致
达维德

0 admin 9 个月前

TI__Guru**** 666710 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Dawid：

CLB 提供了覆盖 ePWM 内各个子模块输出的选项。例如、您可以覆盖 EPWM7动作限定器模块的输出、然后使用 ePWM 的死区模块将死区应用于该输出。

在 C2000Ware 中、我们有使用 CLB 的示例。您需要使用输出覆盖函数来覆盖 ePWM_AQ 输出。

0 admin 9 个月前

TI__Guru**** 666710 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好！
抱歉、我一开始就犯了一个错误、

我的器件实际上是 TMS320F280041、因此很遗憾、它没有 CLB。我必须尝试使用 ePWM 解决方案

0 admin 9 个月前

TI__Guru**** 666710 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Dawid：

我有另一个建议。您可以执行以下配置，而不是使用 EPWM4B SyncOut 来生成 T1事件：

在向下计数时使用 EPWM4 TBCTR=CMPB 来生成 ADCSOCB 信号
通过 ADCSOCOUTSELECT 寄存器使能 EPWM4 ADCSOCBO
在 EPWMXBAR TRIP 4中选择 ADCSOCBO、
选择 Trip 4作为您的 EPWM8 DCAH 活动、
当 DCAH 为高电平时生成 DCAEVT2
选择 DCAEVT2作为您的逐周期跳闸、以将 EPWM8A 输出驱动为低电平。

只要 EPWM4 TBCTR = CMPB 仅在向下计数时、这将有效地导致 EPWM8A 输出变为低电平、因此您无需在运行时更新 EPWM8的操作限定器设置。这种方法的唯一缺点是您将无法在 EPWM8上施加下降沿延迟、因为输出会被跳变区模块覆盖、但上升沿延迟仍然可用。

谢谢！

卢克

C2000™︎ 微控制器（参考译文帖）

C2000™︎ 微控制器（参考译文帖）(Read Only)

[参考译文] TMS320F280041C：基于其他 ePWM 开启和关闭事件控制 ePWM 输出