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[参考译文] TMS320F28386D:C28x 与 CLA 内核之间的数据宽度不同

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请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1296272/tms320f28386d-data-width-different-between-c28x-and-cla-core

器件型号:TMS320F28386D

typedef 结构
{
uint32_t u32Base;
ADC_ClkPrescale eClkPrescale;
ADC_分辨率电子分辨率;
ADC_SignalMode eSignalMode;
ADC_PulseMode ePulseMode;
ADC_IntNumber eAdcIntNum;
ADC_SOCNumber eSockNumber;
} DrvAdcConfig_t;

typedef 枚举
{
ADC_CLK_DIV_1_0 = 0、//!< ADCCLK =(输入时钟)/1.0
ADC_CLK_DIV_2_0 = 2、//!< ADCCLK =(输入时钟)/2.0
ADC_CLK_DIV_2_5 = 3、//!< ADCCLK =(输入时钟)/ 2.5
ADC_CLK_DIV_3_0 = 4、//!< ADCCLK =(输入时钟)/ 3.0
ADC_CLK_DIV_3_5 = 5、//!< ADCCLK =(输入时钟)/3.5
ADC_CLK_DIV_4_0 = 6、//!< ADCCLK =(输入时钟)/4.0
ADC_CLK_DIV_4_5 = 7、//!< ADCCLK =(输入时钟)/4.5
ADC_CLK_DIV_5_0 = 8、//!< ADCCLK =(输入时钟)/ 5.0
ADC_CLK_DIV_5_5 = 9、//!< ADCCLK =(输入时钟)/ 5.5
ADC_CLK_DIV_6_0 = 10、//!< ADCCLK =(输入时钟)/ 6.0
ADC_CLK_DIV_6_5 = 11、//!< ADCCLK =(输入时钟)/ 6.5
ADC_CLK_DIV_7_0 = 12、//!< ADCCLK =(输入时钟)/ 7.0
ADC_CLK_DIV_7_5 = 13、//!< ADCCLK =(输入时钟)/ 7.5
ADC_CLK_DIV_8_0 = 14、//!< ADCCLK =(输入时钟)/ 8.0
ADC_CLK_DIV_8_5 = 15 //!< ADCCLK =(输入时钟)/8.5
}ADC_ClkPrescale;

在 C28x 中、当创建  DrvAdcConfig_t 的实例时、C28x 内核将元素.eClkPrescale 视为16位。

但如果希望在 CLA 中使用该元素、会发现 .eClkPrescale 为32位、并且面临地址对齐问题