[FAQ] [参考译文] [常见问题解答] TMS320F28003x、TMS320F28004x：闪存 API 使用通报/勘误表

/* Implementation details: */

// As shown in below code snippet:
// Call Flash_DisablePrefetch_SW_Workaround() before Fapi_setActiveFlashBank().
// Call Flash_EnablePrefetch_SW_Workaround() after Fapi_setActiveFlashBank().


    //
    // Disable Flash prefetch before Fapi_setActiveFlashBank()
    //
    Flash_DisablePrefetch_SW_Workaround(FLASH0CTRL_BASE);

    //
    // Initialize the Flash banks and FMC for erase and program operations.
    // Fapi_setActiveFlashBank() function sets the Flash banks and FMC for
    // further Flash operations to be performed on the banks.
    //
    oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0);

    if(oReturnCheck != Fapi_Status_Success)
    {
        //
        // Check Flash API documentation for possible errors
        //
        Example_Error(oReturnCheck);
    }

    //
    // Enable Flash prefetch after Fapi_setActiveFlashBank()
    //
    Flash_EnablePrefetch_SW_Workaround(FLASH0CTRL_BASE);
    
/* Below is the code for Flash_DisablePrefetch_SW_Workaround().  */

//*****************************************************************************
//
//! Disables flash prefetch mechanism and adds 7 cycle delay
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************

#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#else
#pragma CODE_SECTION(Flash_DisablePrefetch_SW_Workaround, ".TI.ramfunc");
#endif
void Flash_DisablePrefetch_SW_Workaround(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ASSERT(Flash_isCtrlBaseValid(ctrlBase));

    //
    // Disable flash prefetch
    //
    Flash_disablePrefetch(ctrlBase);

    //
    // Force a pipeline flush to ensure that the write to the last register
    // configured occurs before returning.
    //
    FLASH_DELAY_CONFIG;
}

/* Below is the code for Flash_EnablePrefetch_SW_Workaround()  */

//*****************************************************************************
//
//! Enables flash prefetch mechanism and adds 7 cycle delay
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************

#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#else
#pragma CODE_SECTION(Flash_EnablePrefetch_SW_Workaround, ".TI.ramfunc");
#endif
void Flash_EnablePrefetch_SW_Workaround(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ASSERT(Flash_isCtrlBaseValid(ctrlBase));

    //
    // Disable flash prefetch
    //
    Flash_enablePrefetch(ctrlBase);

    //
    // Force a pipeline flush to ensure that the write to the last register
    // configured occurs before returning.
    //
    FLASH_DELAY_CONFIG;
}