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器件型号：TMS320F28035 主题中讨论的其他器件：controlSUITE
大家好！
当我尝试在我的代码中使用 PI 控制器时、不断出现链接错误。 有人能在这里提问吗？
下面是代码：
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include <math.h>
#include "Solar_F.h"
__interrupt void cpu_timer0_isr(void);
__interrupt void cpu_timer1_isr(void);
void Adc_Config(void);
void EPwm1(void);
void EPwm2(void);
void EPwm3(void);
void gpiosetup (void);
CNTL_PI_F cntl_pi1;
// Global variables
//
Uint16 LoopCount;
Uint16 ConversionCount;
Uint16 Vin[10];
Uint16 Vo[10];
Uint16 Iin[10];
Uint16 Io[10];
float duty1=0.4;
float duty2=0.4;
float duty3=0.5;
float Vin_act,Vo_act, Iin_act,Io_act;
float Gv = 155;
float Gi = 2.5;
Uint16 i;
int16 period = 600;
int16 phase = 300;
void main(void)
{
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.TINT1 = &cpu_timer1_isr;
// PieVectTable.ADCINT1 = &adc_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
//
// Step 4. Initialize all the Device Peripherals:
//
InitAdc(); // For this example, init the ADC
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, 60, 100);
ConfigCpuTimer(&CpuTimer1, 60, 8.33);
CpuTimer0Regs.TCR.all = 0x4000;
CpuTimer1Regs.TCR.all = 0x4000;
IER |= M_INT1;
IER |= M_INT13;
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
PieCtrlRegs.PIEIER1.bit.INTx6 =1;
gpiosetup ();
EPwm1();
EPwm2();
EPwm3();
CNTL_PI_F_init(&cntl_pi1);
cntl_pi1.Ki = (0.1);
cntl_pi1.Kp = (0.2);
cntl_pi1.Umax = (0.25);
cntl_pi1.Umin = (0.025);
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
LoopCount = 0;
ConversionCount = 0;
//
// Configure ADC
// Note: Channel ADCINA4 will be double sampled to workaround the
// ADC 1st sample issue for rev0 silicon errata
//
EALLOW;
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; //ADCINT1 trips after AdcResults latch
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 2; // setup EOC2 to trigger
// ADCINT1 to fire
//
// set SOC0 channel select to ADCINA0 and SOC 1 -A1, SOC 2 -A2, SOC 3 -A3, SOC 4 -A4
// (dummy sample for rev0 errata workaround)
//
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcRegs.ADCSOC1CTL.bit.CHSEL = 1; //set SOC1 channel select to ADCINA1
AdcRegs.ADCSOC2CTL.bit.CHSEL = 2; //set SOC2 channel select to ADCINA2
AdcRegs.ADCSOC3CTL.bit.CHSEL = 3;
AdcRegs.ADCSOC4CTL.bit.CHSEL = 4;
//
// set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1, SOC1,2, 3 then SOC3
//
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 5;
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 5;
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 5;
//
// set SOC0.SOC1,2, 3,4 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC4CTL.bit.ACQPS = 6;
EDIS;
for(;;);
// {
// LoopCount++;
// }
}
__interrupt void cpu_timer0_isr(void)
{
Vin[ConversionCount] = AdcResult.ADCRESULT0;
Vo[ConversionCount] = AdcResult.ADCRESULT1;
Iin[ConversionCount] = AdcResult.ADCRESULT2;
Io[ConversionCount] = AdcResult.ADCRESULT4;
Vin_act=(Vin[ConversionCount]*Gv*3.3)/4095;
Vo_act=(Vo[ConversionCount]*Gv*3.3)/4095;
Iin_act=(Iin[ConversionCount]*Gi*3.3)/4095;
Io_act=(Io[ConversionCount]*Gi*3.3)/4095;
cntl_pi1.Ref = (1.0);
cntl_pi1.Fbk = (0.1);
CNTL_PI_F_FUNC(&cntl_pi1);
// EPwm1Regs.CMPA.half.CMPA = (EPwm1Regs.TBPRD)*duty;
EPwm1Regs.CMPA.half.CMPA = (EPwm1Regs.TBPRD)*duty1;
EPwm2Regs.CMPA.half.CMPA = (EPwm2Regs.TBPRD)*duty2;
// EPwm3Regs.CMPA.half.CMPA = (EPwm3Regs.TBPRD)*duty3;
//
// If 20 conversions have been logged, start over
//
if(ConversionCount == 9)
{
ConversionCount = 0;
}
else
{
ConversionCount++;
}
//
// Clear ADCINT1 flag reinitialize for next SOC
//
if(i==9)
{
i=0;
}
else
{
i++;
}
// AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
CpuTimer0.InterruptCount++;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
return;
}
__interrupt void cpu_timer1_isr(void)
{
EPwm3Regs.CMPA.half.CMPA = (EPwm3Regs.TBPRD)*duty3;
CpuTimer1.InterruptCount++;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
return;
}
void EPwm1()
{
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
// actual*****
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
EPwm1Regs.TBPRD = period/2; // PWM frequency = 1 / period
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTR = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // sync "down-stream"
// Counter Compare Submodule Registers
EPwm1Regs.CMPA.half.CMPA = 0; // set duty 0% initially
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
// Action Qualifier SubModule Registers
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
}
void EPwm2()
{
EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;
// EPwm2Regs.CMPA.half.CMPA = 300; // Set compare A value
EPwm2Regs.TBPRD = period/2; // Set period for ePWM1
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
// EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // sync "down-stream"
//code for phase shift start
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
if ((0 <= phase)&&(phase <= 2))
{
EPwm2Regs.TBPHS.half.TBPHS = (2-phase);
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; // set to count up after sync
}
else if ((2 < phase)&&(phase <= period/2))
{
EPwm2Regs.TBPHS.half.TBPHS = (phase-2);
EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; // set to count down after sync
}
else if ((period/2 < phase)&&(phase <= period))
{
EPwm2Regs.TBPHS.half.TBPHS = (period-phase+2);
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; // set to count up after sync
}
EPwm2Regs.CMPA.half.CMPA = 0;
//code for phase shift end
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
// EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; // Clear PWM1A on CAD
}
void EPwm3()
{
//
EPwm3Regs.TBCTL.bit.CLKDIV = 0x000;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0x001;
EPwm3Regs.TBCTL.bit.CTRMODE = 2;
EPwm3Regs.AQCTLA.all = 0x0060;
EPwm3Regs.AQCTLB.all = 0x0090;
EPwm3Regs.CMPA.half.CMPA = 67; // Set compare A value
EPwm3Regs.TBPRD = 125;
EPwm3Regs.DBFED = 10;
EPwm3Regs.DBRED = 10;
EPwm3Regs.DBCTL.bit.OUT_MODE = 3;
EPwm3Regs.DBCTL.bit.POLSEL = 2;
EPwm3Regs.DBCTL.bit.IN_MODE = 0;
}
void gpiosetup(void)
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A)
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B)
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A)
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B)
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A)
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B)
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;
EDIS;
}
错误：
error: errors encountered during linking; "Example_2803xAdcSoc.out" not built gmake: *** [Example_2803xAdcSoc.out] Error 1 gmake: Target 'all' not remade because of errors.
