[参考译文] TMS320F280039C：CMPSS 输出不在 IT 级别&#39；s 设置的级别

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https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1355011/tms320f280039c-cmpss-output-not-at-the-level-it-s-set

器件型号：TMS320F280039C

尊敬的先生：

对于下面的图片、 CH3是 CTRIPOUTH、CH4是 CMPx_HP 信号。 DACHVALS 设置为2110 (1.7V@3.3V 回波)。从图中可以看到、CTRIPOUTH 在1.72V (V1)左右被触发为高电平、在1.658V (V2)时被触发为低电平、不用作设置值。我们检查所有设置、看起来一切正常。您能帮助提供建议吗？谢谢。

    EALLOW;
    cmpssRegx->COMPCTL.bit.COMPDACE = 1;        //1 Comparator/DAC enabled
    cmpssRegx->COMPCTL.bit.ASYNCLEN = 0;        //Asynchronous comparator output does not feed into OR gate with latched digital filter output
    cmpssRegx->COMPCTL.bit.CTRIPOUTLSEL = 0;    //0 Output of ASYNCH drives CTRIPOUTL
    cmpssRegx->COMPCTL.bit.CTRIPLSEL = 0;       // Output of ASYNCH drives CTRIPL
    cmpssRegx->COMPCTL.bit.COMPLINV = 1;        //1 Output of comparator is inverted
    cmpssRegx->COMPCTL.bit.COMPLSOURCE = 0;     //0 Inverting input of comparator driven by internal DAC
    cmpssRegx->COMPCTL.bit.ASYNCHEN = 0;        //Asynchronous comparator output does not feed into OR gate with latched digital filter output
    cmpssRegx->COMPCTL.bit.CTRIPOUTHSEL = 0;    //2 Output of ASYNCH drives CTRIPOUTH
    cmpssRegx->COMPCTL.bit.CTRIPHSEL = 0;       //2 Output of ASYNCH drives CTRIPH
    cmpssRegx->COMPCTL.bit.COMPHINV = 0;        //0 Output of comparator is not inverted
    cmpssRegx->COMPCTL.bit.COMPHSOURCE = 0;     //0 Inverting input of comparator driven by internal DAC

    cmpssRegx->COMPHYSCTL.bit.COMPHYS = 0;      //Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs.

    cmpssRegx->COMPDACCTL.bit.SWLOADSEL = 0;    //0 DACxVALA is updated from DACxVALS on SYSCLK
    cmpssRegx->COMPDACCTL.bit.SELREF = 0;       //0 VDDA is the voltage reference for the DAC
    cmpssRegx->COMPDACCTL.bit.DACSOURCE = 0;    //0 DACHVALA is updated from DACHVALS
    cmpssRegx->COMPDACCTL.bit.RAMPSOURCE = 1;   //1 EPWM2SYNCPER

    //THRESH must be larger than SAMPWIN/2
    cmpssRegx->CTRIPLFILCTL.bit.THRESH = 2;     //Low filter majority voting threshold
    cmpssRegx->CTRIPLFILCTL.bit.SAMPWIN = 2;    //Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
    cmpssRegx->CTRIPLFILCLKCTL = 12;            //Low filter sample clock prescale. Number of system clocks between samples.

    cmpssRegx->CTRIPLFILCTL.bit.FILINIT = 1;    //Low filter initialization.

    cmpssRegx->CTRIPHFILCTL.bit.THRESH = 2;     //High filter majority voting threshold
    cmpssRegx->CTRIPHFILCTL.bit.SAMPWIN = 2;    //High filter sample window size. Number of samples to monitor is SAMPWIN+1.
    cmpssRegx->CTRIPHFILCLKCTL = 12;            //High filter sample clock prescale. Number of system clocks between samples.

    cmpssRegx->CTRIPHFILCTL.bit.FILINIT = 1;    //High filter initialization.
    EDIS;

1 年多前