[参考译文] TMS320F28374S：TMS320F28374S 上的 SCIB 只能发送消息、但无法接收消息、而 SCIA 完全正常工作。

void scib_gpio54_55_init(void)
{

        EALLOW;

        const uint16_t mux54 = 6;   // GPIO54_MUX = 6:  SCIB_TX
        const uint16_t mux55 = 6;   // GPIO55_MUX = 6:  SCIB_RX

        GpioCtrlRegs.GPBGMUX2.bit.GPIO54 = mux54 / 4;
        GpioCtrlRegs.GPBMUX2.bit.GPIO54  = mux54 % 4;
        GpioCtrlRegs.GPBPUD.bit.GPIO54   = 0;           // 0: enable pull up
        GpioCtrlRegs.GPBDIR.bit.GPIO54   = 1;           // 0:input 1:output

        GpioCtrlRegs.GPBGMUX2.bit.GPIO55 = mux55 / 4;
        GpioCtrlRegs.GPBMUX2.bit.GPIO55  = mux55 % 4;
        GpioCtrlRegs.GPBPUD.bit.GPIO55   = 0;           // 0: enable pull up
        GpioCtrlRegs.GPBDIR.bit.GPIO55   = 0;           // 0:input 1:output

        EDIS;
}

void scia_gpio35_36_init(void)
{
        EALLOW;

        const uint16_t mux35 = 1;   // GPIO35_MUX = 1:  SCIA_RX
        const uint16_t mux36 = 1;   // GPIO36_MUX = 1:  SCIA_TX

        // SCIA_RX
        GpioCtrlRegs.GPBGMUX1.bit.GPIO35 = mux35 / 4;    // 0:GPIO 1:RXD
        GpioCtrlRegs.GPBMUX1.bit.GPIO35  = mux35 % 4;    // 0:GPIO 1:RXD
        GpioCtrlRegs.GPBPUD.bit.GPIO35   = 0;    // enable pull up
        GpioCtrlRegs.GPBDIR.bit.GPIO35   = 0;    // 0:input 1:output

        // SCIA_TX
        GpioCtrlRegs.GPBGMUX1.bit.GPIO36 = mux36 / 4;   // 0:GPIO 1:TXD
        GpioCtrlRegs.GPBMUX1.bit.GPIO36  = mux36 % 4;   // 0:GPIO 1:TXD
        GpioCtrlRegs.GPBPUD.bit.GPIO36   = 0;    // enable pull up
        GpioCtrlRegs.GPBDIR.bit.GPIO36   = 1;    // 0:input 1:output

        EDIS;
}

void scib_init(uint32_t baud_rate)
{
        uint16_t prescale = (uint16_t)(get_clock_freq() / 4 / baud_rate / 8 - 1);

        ScibRegs.SCICTL1.all             = 0x00;                // reset SCI
        ScibRegs.SCICCR.all              = 0x07;                // 1 bit stop, disable parity, idle mode, 8 bits data
        ScibRegs.SCIHBAUD.bit.BAUD       = prescale / 256;
        ScibRegs.SCILBAUD.bit.BAUD       = prescale % 256;
        ScibRegs.SCIFFRX.bit.RXFIFORESET = 1;                   // 1:enable RXFIFO
        ScibRegs.SCIFFTX.bit.SCIRST      = 1;                   // 1:resume FIFO, 0: reset FIFO
        ScibRegs.SCIFFTX.bit.SCIFFENA    = 1;                   // enable FIFO
        ScibRegs.SCICTL1.all             = 0x23;                // Enable RX and TX, enable SCI

        add_task("scib_soft_fifo", soft_fifo_1ms_task, FOREGROUND_TASK, 1, 0);
}

static void soft_fifo_1ms_task(void)
{
        uint16_t i;

        // --------------------------------------------------------------------
        if(ScibRegs.SCIRXST.bit.RXERROR)
        {
                // writing a zero to SWRESET to clear FE OE PE RXERROR
                ScibRegs.SCICTL1.bit.SWRESET = 0;
                // re-enable SCI by writing a 1 to SWRESET bit
                ScibRegs.SCICTL1.bit.SWRESET = 1;
        }

        // --------------------------------------------------------------------
        while(ScibRegs.SCIFFRX.bit.RXFFST)
        {
                uint8_t rxd = ScibRegs.SCIRXBUF.bit.SAR;

                if(ScibRxFifo.ElementNum < 2*ArrLen(ScibRxFifo.Buffer))
                {
                        packed_byte_array_set(ScibRxFifo.Buffer,
                                        ScibRxFifo.EnqueueIndex,
                                        rxd);

                        ScibRxFifo.EnqueueIndex ++;
                        ScibRxFifo.EnqueueIndex %= 2*ArrLen(ScibRxFifo.Buffer);
                        ScibRxFifo.ElementNum   ++;
                }
        }

        // --------------------------------------------------------------------
        for(i=0; i<16; i++)
        {
                if(ScibRegs.SCIFFTX.bit.TXFFST < 16)
                {
                        uint8_t txd;

                        if(ScibTxFifo.ElementNum)
                        {
                                txd = packed_byte_array_get(ScibTxFifo.Buffer, ScibTxFifo.DequeueIndex);

                                ScibTxFifo.DequeueIndex ++;
                                ScibTxFifo.DequeueIndex %= 2*ArrLen(ScibTxFifo.Buffer);
                                ScibTxFifo.ElementNum   --;

                                ScibRegs.SCITXBUF.bit.TXDT = txd;
                        }
                }
                else
                {
                        break;
                }
        }
}

void scia_init(uint32_t baud_rate)
{
        uint16_t prescale = (uint16_t)(get_clock_freq() / 4 / baud_rate / 8 - 1);

        SciaRegs.SCICTL1.all             = 0x00;                // reset SCI
        SciaRegs.SCICCR.all              = 0x07;                // 1 bit stop, disable parity, idle mode, 8 bits data
        SciaRegs.SCIHBAUD.bit.BAUD       = prescale / 256;
        SciaRegs.SCILBAUD.bit.BAUD       = prescale % 256;
        SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;                   // 1:enable RXFIFO
        SciaRegs.SCIFFTX.bit.SCIRST      = 1;                   // 1:resume FIFO, 0: reset FIFO
        SciaRegs.SCIFFTX.bit.SCIFFENA    = 1;                   // enable FIFO
        SciaRegs.SCICTL1.all             = 0x23;                // Enable RX and TX, enable SCI

        add_task("scia_soft_fifo", soft_fifo_1ms_task, FOREGROUND_TASK, 1, 0);
}

static void soft_fifo_1ms_task(void)
{
        uint16_t i;

        // --------------------------------------------------------------------
        if(SciaRegs.SCIRXST.bit.RXERROR)
        {
                // writing a zero to SWRESET to clear FE OE PE RXERROR
                SciaRegs.SCICTL1.bit.SWRESET = 0;
                // re-enable SCI by writing a 1 to SWRESET bit
                SciaRegs.SCICTL1.bit.SWRESET = 1;
        }

        // --------------------------------------------------------------------
        while(SciaRegs.SCIFFRX.bit.RXFFST)
        {
                uint8_t rxd = SciaRegs.SCIRXBUF.bit.SAR;

                if(SciaRxFifo.ElementNum < 2*ArrLen(SciaRxFifo.Buffer))
                {
                        packed_byte_array_set(SciaRxFifo.Buffer,
                                        SciaRxFifo.EnqueueIndex,
                                        rxd);

                        SciaRxFifo.EnqueueIndex ++;
                        SciaRxFifo.EnqueueIndex %= 2*ArrLen(SciaRxFifo.Buffer);
                        SciaRxFifo.ElementNum   ++;
                }
        }

        // --------------------------------------------------------------------
        for(i=0; i<16; i++)
        {
                if(SciaRegs.SCIFFTX.bit.TXFFST < 16)
                {
                        uint8_t txd;

                        if(SciaTxFifo.ElementNum)
                        {
                                txd = packed_byte_array_get(SciaTxFifo.Buffer, SciaTxFifo.DequeueIndex);

                                SciaTxFifo.DequeueIndex ++;
                                SciaTxFifo.DequeueIndex %= 2*ArrLen(SciaTxFifo.Buffer);
                                SciaTxFifo.ElementNum   --;

                                SciaRegs.SCITXBUF.bit.TXDT = txd;
                        }
                }
                else
                {
                        break;
                }
        }
}