[参考译文] TMS320F28335：McBSP 用作与 HOLT 的 SPI 通信(HI-35850)

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请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1447514/tms320f28335-mcbsp-used-as-spi-communication-with-holt-hi-35850

器件型号：TMS320F28335

工具与软件：

您好！

我们的项目涉及在 SPI 模式下配置 McBSP 以在 SPI 模式下与 ARINC 429卡(HI-35850)通信

为配置 McBSP、下面是我们在 SPI 从模式下将 HI-35850配置为主模式下的 McBSP 配置

随附了代码和波形、即使波形似乎正确、我们从 Holt 器件的主复位得到的响应为00、而不是09。

所以请提出改进的建议。

#include "Mcu1_Device.h"
#include "Mcu1_Gpio.h"
#include "stdio.h"
#include "DSP2833x_Mcbsp.h"
#include "Mcu1_PieVect.h"
#include "Mcu1_SysCtrl.h"

/*For SPI McBsp*/
void init_mcbsp_spi(void);
void mcbsp_xmit(int a);
void error(void);

// Global data for this example
UNS16 sdata1 ;    
UNS16 rdata1;    

UNS16 sdata2;   
UNS16 rdata2;    
UNS16 sdata3;    
UNS16 sdata4;
UNS16 sdata5;
UNS16 sdata6 ;
UNS16 sdata7;

void main(void)
{
//    printf("Enter main\n");
    /*Initialize System Control:PLL, WatchDog*/
    InitSysCtrl();
    InitMcbspaGpio();
    /* Disable CPU interrupts*/
    DINT;

/*****************************************************************************/
/* Initialize the PIE control registers to their default state.*/
/* The default state is all PIE interrupts disabled and flags
   are cleared.*/
/******************************************************************************/
    InitPieCtrl();
    /* Disable all interrupts and clear all interrupt flags:*/
     IER = 0x0000;
     IFR = 0x0000;

/******************************************************************************/
/* Initialize the PIE vector table with pointers to the shell Interrupt
    Service Routines (ISR).*/
/* This will populate the entire table, even if the interrupt
    is not used in this.  This is useful for debug purposes.*/
/******************************************************************************/

    InitPieVectTable();

    init_mcbsp_spi();
UNS16 dummy_read = 0x0000;
    sdata1 = 0x0100;  // Master Reset 
    sdata2 = 0x0A00;  // Read the Status Register
    sdata3 = 0x0000;  //Dummy Read 

    sdata4 = 0x1000; // Config Control Register 
    sdata5 = 0x2000;  // Config Control Register 
    sdata6 = 0x2000;  //Config Control Register 

    sdata7 = 0x0B00;  //Read Control Register 

    int i;
    int j;
    for(i=0;i<100;i++)

/******* Master reset************** */
    mcbsp_xmit(sdata1);    
    while( McbspaRegs.SPCR1.bit.RRDY == 0 ) {}      

    //Dummy Read
    dummy_read = McbspaRegs.DRR1.all;
    printf("TX data1:%x\n",sdata1);

    /*Config OPCODE */

    mcbsp_xmit(sdata4);   // 1000 Opcode Config
    mcbsp_xmit(sdata5);   // 2000 Opcode Config
    mcbsp_xmit(sdata6);   // 2000 Opcode Config

    while( McbspaRegs.SPCR1.bit.RRDY == 0 ) {}

    dummy_read = McbspaRegs.DRR1.all;    // Dummy Read
    dummy_read = McbspaRegs.DRR1.all;    // Dummy Read
    dummy_read = McbspaRegs.DRR1.all;    // Dummy Read
    for(j=0;j<=10000;j++)     //Delay
                {

                }

/**************Read Status Register*************************/
    mcbsp_xmit(sdata2);  //Read the Status Register
    mcbsp_xmit(sdata3);  //Read Dummy data

    for(j=0;j<=350;j++)
            {

            }

    dummy_read = McbspaRegs.DRR1.all;
    rdata1 = McbspaRegs.DRR1.all;                     

    printf("TX data2:%X\n",sdata2);
    printf("Received data2:%x\n",rdata1);

/**************Read Control register*************************/
    mcbsp_xmit(sdata7);  //0B
    mcbsp_xmit(sdata2); //00
    mcbsp_xmit(sdata2);  //00
    while( McbspaRegs.SPCR1.bit.RRDY == 0 ) {}

    dummy_read = McbspaRegs.DRR1.all;  //Read Dummy data
    dummy_read = McbspaRegs.DRR1.all;   //Read Dummy data
    dummy_read = McbspaRegs.DRR1.all;   //Read Dummy data
    rdata2 = McbspaRegs.DRR1.all;
    for(j=0;j<=350;j++)
                 {

                 }

    printf("TX data 0B:%X\n",sdata7);
    printf("Received data for 0B:%x\n",dummy_read);
    printf("Received data for 0B:%x\n",rdata2);

    for(j=0;j<=350;j++)
        {

        }

           }

   }

/*************Config McBSP**********************/
   void init_mcbsp_spi()
   {


       // McBSP-A register settings
           McbspaRegs.SPCR2.all=0x0000;         // Reset FS generator, sample rate generator & transmitter
           McbspaRegs.SPCR1.all=0x0000;         // Reset Receiver, Right justify word, Digital loopback dis.
           McbspaRegs.PCR.all=0x0F08;           //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1)
           McbspaRegs.SPCR1.bit.DLB = 0;
           McbspaRegs.SPCR1.bit.CLKSTP = 3;     // Together with CLKXP/CLKRP determines clocking scheme
           McbspaRegs.PCR.bit.CLKXP = 0;        // CPOL = 0, CPHA = 0 rising edge no delay
           McbspaRegs.PCR.bit.CLKRP = 1;

           McbspaRegs.RCR2.bit.RDATDLY=01;      // FSX setup time 1 in master mode. 0 for slave mode (Receive)
           McbspaRegs.XCR2.bit.XDATDLY=01;      // FSX setup time 1 in master mode. 0 for slave mode (Transmit)

           McbspaRegs.RCR1.bit.RWDLEN1=0;       // 32-bit word
           McbspaRegs.XCR1.bit.XWDLEN1=0;       // 32-bit word

           McbspaRegs.SRGR2.all=0x2000;         // CLKSM=1, FPER = 1 CLKG periods
           McbspaRegs.SRGR1.all= 0x000F;        // Frame Width = 1 CLKG period, CLKGDV=16

           McbspaRegs.SPCR2.bit.GRST=1;         // Enable the sample rate generator
           delay_loop();                        // Wait at least 2 SRG clock cycles

           McbspaRegs.SPCR2.bit.XRST=1;         // Release TX from Reset
           McbspaRegs.SPCR1.bit.RRST=1;         // Release RX from Reset
           McbspaRegs.SPCR2.bit.FRST=1;         // Frame Sync Generator reset
   }

   void mcbsp_xmit(int a)
      {
          McbspaRegs.DXR1.all=a;
      }
/******************************************************************************/
/* End of file */
/******************************************************************************/