[参考译文] TMS320F28388D：DMA 复制后的第一个采样为0

void ConfigureADC(void)
{
EALLOW;

// Set ADC clock prescaler to divide by 4 (50MHz ADC clock)
AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
AdccRegs.ADCCTL2.bit.PRESCALE = 6;
AdcdRegs.ADCCTL2.bit.PRESCALE = 6;

// Set pulse positions to late
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;

// Configure ADC SOC0 for each ADC
// ADC-A SOC0 Configuration
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 13; // ePWM5 SOCA trigger
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 3; // ADCINA3 channel
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; // Acquisition window

AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 14; // ePWM5 SOCB trigger
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 3; // ADCINA1 (or any channel)
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 14; // Sample window

// ADC-B SOC1 Configuration
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 13; // ePWM5 SOCA trigger
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 3; // ADCINB3 channel
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 14; // Acquisition window

AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 14; // ePWM5 SOCA trigger
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3; // ADCINB3 channel
AdcbRegs.ADCSOC1CTL.bit.ACQPS = 14; // Acquisition window

// ADC-C SOC0 Configuration
AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 13; // ePWM5 SOCA trigger
AdccRegs.ADCSOC0CTL.bit.CHSEL = 3; // ADCINC3 channel
AdccRegs.ADCSOC0CTL.bit.ACQPS = 14; // Acquisition window

// ADC-C SOC1 Configuration
AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 14; // ePWM5 SOCA trigger
AdccRegs.ADCSOC1CTL.bit.CHSEL = 3; // ADCINC3 channel
AdccRegs.ADCSOC1CTL.bit.ACQPS = 14; // Acquisition window


// ADC-D SOC0 Configuration
AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 13; // ePWM5 SOCA trigger
AdcdRegs.ADCSOC0CTL.bit.CHSEL = 3; // ADCIND3 channel
AdcdRegs.ADCSOC0CTL.bit.ACQPS = 14; // Acquisition window

// ADC-D SOC1 Configuration
AdcdRegs.ADCSOC1CTL.bit.TRIGSEL = 14; // ePWM5 SOCA trigger
AdcdRegs.ADCSOC1CTL.bit.CHSEL = 3; // ADCIND3 channel
AdcdRegs.ADCSOC1CTL.bit.ACQPS = 14; // Acquisition window

// Select SOC1 as interrupt source and enable interrupts for each ADC
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 1; // EOC1 triggers ADCINT1
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable ADCINT1
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear interrupt flag
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1;

// Disable ADC interrupts for other ADCs (since we're using DMA)
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 0;
AdccRegs.ADCINTSEL1N2.bit.INT1E = 0;
AdcdRegs.ADCINTSEL1N2.bit.INT1E = 0;

// Power up ADC modules
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up ADC-A
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up ADC-B
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up ADC-C
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up ADC-D

// Delay for 1 ms to allow ADCs to power up
DELAY_US(1000);

EDIS;
}

void DMAInit(void)
{
    // Initialize DMA
    DMAInitialize();

    /* The Burst size is BUFFER_SIZE/2 because we are setting up the DMA in 32 bits
    *  mode. And each burst will transfer 2 adc samples of 16 bit each.
    */
    DMACH1AddrConfig(&state.activeAdcBuffer->adcA_buffer[0], &AdcaResultRegs.ADCRESULT0);  // ADC-A buffer
    DMACH1BurstConfig(1, 0, 2);  // Common burst configuration
    DMACH1TransferConfig((BUFFER_SIZE/2)-1, 0, 2);  // Common transfer configuration
    DMACH1ModeConfig(
            DMA_ADCAINT1, PERINT_ENABLE, ONESHOT_DISABLE, CONT_DISABLE, SYNC_DISABLE,
        SYNC_SRC, OVRFLOW_DISABLE, THIRTYTWO_BIT, CHINT_END, CHINT_ENABLE
    );

    // DMA setup for ADC-A (Channel 2)
    DMACH2AddrConfig(&state.activeAdcBuffer->adcA_buffer[0], &AdcaResultRegs.ADCRESULT0);  // ADC-A buffer
    DMACH2BurstConfig(1, 0, 2);  // Common burst configuration
    DMACH2TransferConfig((BUFFER_SIZE/2)-1, 0, 2);  // Common transfer configuration
    DMACH2ModeConfig(
        DMA_ADCAINT1, PERINT_ENABLE, ONESHOT_DISABLE, CONT_DISABLE, SYNC_DISABLE,
        SYNC_SRC, OVRFLOW_DISABLE, THIRTYTWO_BIT, CHINT_END, CHINT_ENABLE
    );

    // DMA setup for ADC-B (Channel 3)
    DMACH3AddrConfig(&state.activeAdcBuffer->adcB_buffer[0], &AdcbResultRegs.ADCRESULT0);  // ADC-B buffer
    DMACH3BurstConfig(1, 0, 2);  // Common burst configuration
    DMACH3TransferConfig((BUFFER_SIZE/2)-1, 0, 2);  // Common transfer configuration
    DMACH3ModeConfig(
        DMA_ADCAINT1, PERINT_ENABLE, ONESHOT_DISABLE, CONT_DISABLE, SYNC_DISABLE,
        SYNC_SRC, OVRFLOW_DISABLE, THIRTYTWO_BIT, CHINT_END, CHINT_ENABLE
    );

    // DMA setup for ADC-C (Channel 4)
    DMACH4AddrConfig(&state.activeAdcBuffer->adcC_buffer[0], &AdccResultRegs.ADCRESULT0);  // ADC-C buffer
    DMACH4BurstConfig(1, 0, 2);  // Common burst configuration
    DMACH4TransferConfig((BUFFER_SIZE/2)-1, 0, 2);  // Common transfer configuration
    DMACH4ModeConfig(
        DMA_ADCAINT1, PERINT_ENABLE, ONESHOT_DISABLE, CONT_DISABLE, SYNC_DISABLE,
        SYNC_SRC, OVRFLOW_DISABLE, THIRTYTWO_BIT, CHINT_END, CHINT_ENABLE
    );

    // DMA setup for ADC-D (Channel 5)
    DMACH5AddrConfig(&state.activeAdcBuffer->adcD_buffer[0], &AdcdResultRegs.ADCRESULT0);  // ADC-D buffer
    DMACH5BurstConfig(1, 0, 2);  // Common burst configuration
    DMACH5TransferConfig((BUFFER_SIZE/2)-1, 0, 2);  // Common transfer configuration
    DMACH5ModeConfig(
        DMA_ADCAINT1, PERINT_ENABLE, ONESHOT_DISABLE, CONT_DISABLE, SYNC_DISABLE,
        SYNC_SRC, OVRFLOW_DISABLE, THIRTYTWO_BIT, CHINT_END, CHINT_ENABLE
    );
}