[参考译文] TMS320F28377S：SPI 和 DMA 接收卡滞

void sInitDma(void)
{
    // refer to dma.c for the descriptions of the following functions.


    //Initialize DMA
    DMAInitialize();


    DMA4Addr = (volatile INT16U *)Test4;
    DMA5Addr = (volatile INT16U *)Test2;
    DMA6Addr = (volatile INT16U *)Test1;


    // configure DMACH4  for spib TX
    DMACH4AddrConfig(&SpibRegs.SPITXBUF, DMA4Addr);   //
    DMACH4BurstConfig(7, 1, 0);           // Burst size, src step, dest step
    DMACH4TransferConfig(127, 1, 0);      // transfer size, src step, dest step
    DMACH4ModeConfig(DMA_SPIBTX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,\
            SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);


    // configure DMACH5  for spib RX
    DMACH5AddrConfig(DMA5Addr, &SpibRegs.SPIRXBUF);   //
    DMACH5BurstConfig(7, 0, 1);          //  size, src step, dest step
    DMACH5TransferConfig(127, 0, 1);     // transfer size, src step, dest step
    DMACH5ModeConfig(DMA_SPIBRX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,\
            SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);


    // configure DMA CH6 for spia TX
    DMACH6AddrConfig(&SpiaRegs.SPITXBUF, DMA6Addr);
    DMACH6BurstConfig(7, 1, 0);
    DMACH6TransferConfig(127, 1, 0);
    DMACH6ModeConfig(DMA_SPIATX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,\
            SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);




    // Ensure DMA is connected to Peripheral Frame 2 bridge (EALLOW protected)
    EALLOW;
    CpuSysRegs.SECMSEL.bit.PF2SEL = 1;
    EDIS;


    EALLOW;
    DmaRegs.CH4.CONTROL.bit.RUN = 0;
    DmaRegs.CH5.CONTROL.bit.RUN = 0;
    DmaRegs.CH6.CONTROL.bit.RUN = 0;
    EDIS;


    //Enable DMA interrupt
    PieCtrlRegs.PIEIER7.bit.INTx4 = 0;      // Disable INT7.4
    PieCtrlRegs.PIEIER7.bit.INTx5 = 1;      // Enable PIE Group 7, INT 5 (DMA CH5)
    PieCtrlRegs.PIEIER7.bit.INTx6 = 1;      // Enable PIE Group 7, INT 6 (DMA CH6)
    IER |= M_INT7;                          // Enable CPU INT6
}

void SpiBFifo(void)
{
    INT16U m;


    // FIFO configuration
    SpibRegs.SPIFFCT.all=0x0;               // place SPI in reset
    for(m=0;m<3;m++);
    SpibRegs.SPIFFRX.all=0x2040;            // RX FIFO enabled, clear FIFO int
    SpibRegs.SPIFFRX.bit.RXFFIL = 8;        // Set RX FIFO level
    SpibRegs.SPIFFTX.all=0xE040;            // FIFOs enabled, TX FIFO released,
    SpibRegs.SPIFFTX.bit.TXFFIL = 8;        // Set TX FIFO level

    // SPI configuration
    SpibRegs.SPICCR.all = 0x0007;//0x000F;  //Reset off, rising edge, 16-bit char bits
    SpibRegs.SPICTL.all = 0x000e;           //Enable master mode, delayed phase, enable talk, and SPI int disabled.

    SpibRegs.SPIBRR.all = 0x0006;
    SpibRegs.SPISTS.all = 0x0000;
    SpibRegs.SPIPRI.bit.FREE = 0x0001;      //Transmission not affected by emulator
    SpibRegs.SPICCR.bit.SPISWRESET=1;       
}

// INT7.5
void DMAIntCh5ISR(void)       // DMA Ch5
{
    EALLOW;                                 // NEED TO EXECUTE EALLOW INSIDE ISR !!!
    DmaRegs.CH5.CONTROL.bit.HALT=1;
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // ACK to receive more interrupts from this PIE group
    EDIS;
}