[参考译文] F28M35H52C：ePWM 问题

//This is code for setting up in the C28 Main()

    Uint16 Period = 37500;

    InitSysCtrl(); 

    EALLOW; 
    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = ePWM1A 
    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = ePWM1B 
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = ePWM2A 
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = ePWM2B 
    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = ePWM3A 
    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = ePWM3B 
    GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // GPIO6 = ePWM4A 
    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // GPIO7 = ePWM4B 
    GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // GPIO8 = ePWM5A 
    GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // GPIO9 = ePWM5B 
    GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // GPIO10 = ePWM6A 
    GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // GPIO11 = ePWM6B 
    EDIS; 

    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); 

    InitFlash();       

    EPwm1Regs.TBCTL.all = 0;        // clear all bits in TBCTL
    EPwm1Regs.TBCTL.bit.CLKDIV = 0;     // CLKDIV = “div by 1”;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;  // HSPCLKDIV = “div by 1”
    EPwm1Regs.TBCTL.bit.CTRMODE = 2;    // count mode = up-down mode
    EPwm1Regs.AQCTLA.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm1Regs.AQCTLB.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm1Regs.TBPRD = Period;            // 2 kHz PWM frequency

    EPwm2Regs.TBCTL.all = 0;        // clear all bits in TBCTL
    EPwm2Regs.TBCTL.bit.CLKDIV = 0;     // CLKDIV = “div by 1”;
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;  // HSPCLKDIV = “div by 1”
    EPwm2Regs.TBCTL.bit.CTRMODE = 2;    // count mode = up-down mode
    EPwm2Regs.AQCTLA.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm2Regs.AQCTLB.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm2Regs.TBPRD = Period;            // 2 kHz PWM frequency

    EPwm3Regs.TBCTL.all = 0;        // clear all bits in TBCTL
    EPwm3Regs.TBCTL.bit.CLKDIV = 0;     // CLKDIV = “div by 1”;
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;  // HSPCLKDIV = “div by 1”
    EPwm3Regs.TBCTL.bit.CTRMODE = 2;    // count mode = up-down mode
    EPwm3Regs.AQCTLA.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm3Regs.AQCTLB.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm3Regs.TBPRD = Period;            // 2 kHz PWM frequency

    EPwm4Regs.TBCTL.all = 0;        // clear all bits in TBCTL
    EPwm4Regs.TBCTL.bit.CLKDIV = 0;     // CLKDIV = “div by 1”;
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0;  // HSPCLKDIV = “div by 1”
    EPwm4Regs.TBCTL.bit.CTRMODE = 2;    // count mode = up-down mode
    EPwm4Regs.AQCTLA.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm4Regs.AQCTLB.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm4Regs.TBPRD = Period;            // 2 kHz PWM frequency

    EPwm5Regs.TBCTL.all = 0;        // clear all bits in TBCTL
    EPwm5Regs.TBCTL.bit.CLKDIV = 0;     // CLKDIV = “div by 1”;
    EPwm5Regs.TBCTL.bit.HSPCLKDIV = 0;  // HSPCLKDIV = “div by 1”
    EPwm5Regs.TBCTL.bit.CTRMODE = 2;    // count mode = up-down mode
    EPwm5Regs.AQCTLA.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm5Regs.AQCTLB.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm5Regs.TBPRD = Period;            // 2 kHz PWM frequency

    EPwm6Regs.TBCTL.all = 0;        // clear all bits in TBCTL
    EPwm6Regs.TBCTL.bit.CLKDIV = 0;     // CLKDIV = “div by 1”;
    EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0;  // HSPCLKDIV = “div by 1”
    EPwm6Regs.TBCTL.bit.CTRMODE = 2;    // count mode = up-down mode
    EPwm6Regs.AQCTLA.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm6Regs.AQCTLB.all = 0x0006;      // ZRO=set; PRD=clear
    EPwm6Regs.TBPRD = Period;            // 2 kHz PWM frequency
    
    
    
    
    
    //This is the code from the M3 Main()
    
    HWREG(SYSCTL_MWRALLOW) =  0xA5A5A5A5;

    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

    FlashInit();
    
  IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH);
  
  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
  
  GPIOPinConfigureCoreSelect(GPIO_PORTA_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);