请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。
器件型号：AFE7950EVM 主题中讨论的其他器件： AFE7950、TRF1208、 TRF1208EVM
工具/软件：
您好、先生/ Ma'am、
借助 AFE7950EVM 和 MPF300t (FPGA)、我们建立了串行器/解串器链路并能够在这些链路之间传输数据。 但问题是我们尝试使用 Latte 软件发送图形数据时、频率会发生漂移、如以下视频所述：
e2e.ti.com/.../VID_5F00_20250403_5F00_153650-_2800_1_2900_.mp4
使用的代码固定在下面：
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_14810; Data Rate = 122.88M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_14810; Data Rate = 122.88M
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
sysParams.RRFMode = 0 # RRF 0: 4T4R2F FDD Mode
sysParams.enableDacInterleavedMode=False
############## Digital Chain ##############
##### RX #####
sysParams.ddcFactorRx = [24,24,24,24] #DDC decimation factor for RX A, B, C and D
sysParams.rxNco0 = [[9500,9500], #Band0, Band1 for RXA
[9500,9500], #Band0, Band1 for RXB
[9500,9500], #Band0, Band1 for RXC
[9500,9500]] #Band0, Band1 for RXD
##### FB #####
sysParams.ddcFactorFb = [6,6] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [4000,4000] #Band0 for FB1 and FB2
sysParams.fbEnable = [False,False]
##### TX #####
sysParams.ducFactorTx = [96,96,96,96] #DUC interpolation factor for TX A, B, C and D
sysParams.txNco0 = [[9500,9500], #Band0, Band1 for TXA
[9500,9500], #Band0, Band1 for TXB
[9500,9500], #Band0, Band1 for TXC
[9500,9500]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["14810","14810","14810","14810"]
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.rxJesdTxScr = [False,False,False,False]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [8,8,8,8]
sysParams.fbJesdTxK = [8,8]
sysParams.jesdTxLaneMux = [7,1,2,3,6,5,4,0] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2T,
# this should be [[1,0,2,3],[5,4,6,7]]
##### DAC-JESD #####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx = ["14810","14810","14810","14810"]
sysParams.jesdRxLaneMux = [6,4,2,3,7,5,1,0] #[7,6,2,3,4,5,1,0] #0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2R
# this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd = [3, 3]
sysParams.jesdRxScr = [False,False,False,False]
sysParams.jesdRxK = [8, 8, 8, 8]
##### JESD Common #####
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
############## LMK Params ##############
lmkParams.pllEn = True
lmkParams.inputClk = 1474.56 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 245.76 # Should be equal to LaneRate/40 for TSW14J56
############## Logging ##############
#logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Piersight_4000.txt")
#logDumpInst.logFormat=0x0
logDumpInst.logFormat=0x01
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
#line 119 changes ps
sysParams.useSpiSysref=True
AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15) # bit-wise; 4R,2F,4T
for i in [0,1]:
for j in [0,1]:
AFE.JESD.DACJESD[i].dacJesdConstantTestPatternValue(1,j,0,32767,0) # enable, channelNum, bandNum, Ival, Qval
我们验证 PLL 已锁定(通过读取0x66寄存器、变为0x33 (value))。
这种漂移会给我们造成重大问题。 请检查这个问题。
谢谢、此致
Akula Vamsi
Piersight Space
数字设计工程师
