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https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/575665/phase-noise-of-lmk04828
对于以下设置，相位噪声是多少？
PLL=lmk0.4828万
外部VCO频率125MHz
输出频率 2.5GHz (LVDS/LVPECL)
谢谢
在模拟中有些事情不太正确。 但是，到目前为止，在时钟架构中设置双循环模拟有点模糊。 请查找随附的文档以帮助进行双环模拟。 它还将展示实现最佳性能。
e2e.ti.com/.../Using-Clock-Architect-for-Dual-Loop-PLLs_2C00_-2017_2D00_02_2D00_20.pdf
