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https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/712893/cdcv304-output-signal-duty-cycle-is-different-from-input-signal
大家好、团队成员
我的通信客户在其 RRU 和 AAU 产品中使用 CDCV304。 输入信号为133MHz 时钟、占空比为50%、但输出时钟的占空比更改为40%。
您能否分享此问题的任何可能原因？ 如何解决？
输入时钟信号波形、133MHz、50%占空比：
输出时钟信号波形、133MHz、40%占空比：
谢谢
Kevin
