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https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/608103/ads1271-stm32f429-timer-pwm-output-signal-used-as-ads1271-clk
下面是时钟配置
然后是我们采样的波形
fSCLK/fCLK 比率为0.75
如上一张图片所示、频域有一些干扰、我发现 原因是 SPI 中断接收功能 丢失了一些点。
