[参考译文] AMC1204：有关累加器的阐述

尊敬的 Michele：

为什么要减1 DELTA1？ 该代码基于图13、应保持一致。 如果有理由需要减小 DELTA1、您始终可以复制并修改它、使其最适合您的应用程序。 请告诉我。

此致、
评估

很抱歉 Eva,自从我不使用 VHDL 以来已经过去了很多年了,我仍在尝试模拟模块...

首先、我对 FF1的+/-输入 感到困惑。。。

它看起来是这样的触发器、然后我期望 DELTA1作为 STD_LOGIC、但看一下 VHDL 代码、它似乎是由于 STD_LOGIC_VECTOR 而产生的加法计数器。

总线宽度为25位、那么它是25位 sinc3滤波器还是需要保持额外位的24位滤波器？

在原理图上只能看到2个积分器块、而3个微分器块不应该成对、那么3个和3个都不应该成对？

MMH…… 我进行了仿真、我不知道我错了什么...

我创建了 SDO 信号模拟调制器输出、SCK 是基准时钟、而 SCk4是抽取器的输出时钟。
第一部分是正斜率、其中 SDO 从00000000开始... 至...11111111 (SBAA094的图3)、然后再次返回到00000。

我希望 CN5从0000开始、增加到正值(正斜率结束)、然后返回到0000。

此处使用的代码：

-- sinc3 vhdl code from SBAA094


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;



entity FLT is



port(RESN, MOUT, MCLK, CNR : in std_logic;
                       CN5 : out std_logic_vector(4 downto 0)
);

end FLT;


architecture RTL of FLT is
 signal DN0, DN1, DN3, DN5 : std_logic_vector(4 downto 0);
 signal CN1, CN2, CN3, CN4 : std_logic_vector(4 downto 0);
 signal DELTA1 : std_logic_vector(4 downto 0);

 begin
 process(MCLK, RESn)
    begin
       if RESn = '0' then
          DELTA1 <= (others => '0');

       elsif MCLK'event and MCLK = '1' then
 
          if MOUT = '1' then
             DELTA1 <= DELTA1 + 1;
          end if;
       end if;
    end process;
 


 process(RESN, MCLK)
    begin
       if RESN = '0' then
          CN1 <= (others => '0');
          CN2 <= (others => '0');
       elsif MCLK'event and MCLK = '1' then
          CN1 <= CN1 + DELTA1;
          CN2 <= CN2 + CN1;
       end if;
    end process;
 


process(RESN, CNR)
   begin
      if RESN = '0' then
         DN0 <= (others => '0');
         DN1 <= (others => '0');
         DN3 <= (others => '0');
         DN5 <= (others => '0');
      elsif CNR'event and CNR = '1' then
         DN0 <= CN2;
         DN1 <= DN0;
         DN3 <= CN3;
         DN5 <= CN4;
      end if;
   end process;
 
   CN3 <= DN0 - DN1;
   CN4 <= CN3 - DN3;
   CN5 <= CN4 - DN5;
end RTL;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

-- per le funzioni di output su console
use STD.textio.all;                     -- basic I/O
use IEEE.std_logic_textio.all;          -- I/O for logic types


entity sinc_filter is
end sinc_filter;

architecture Behavioral of sinc_filter is



signal sck, sck4 : std_logic; -- clock signals: sck = clock signal from modulator, sck4 = clock signal for output sampling frequency
signal SDO :std_logic; -- output signal from modulator
signal reset : std_logic; -- reset signal
signal CN5 : std_logic_vector(4 downto 0); -- sinc3 output




-- for debug
constant DataWidth : integer := 6; -- larghezza in bit del bus
signal a_slv : std_logic_vector((DataWidth-1) downto 0); -- se DataWidth  is 5 , allora a_slv va da 4 a 0 (5 bit)
signal sck2 :std_logic;
signal w : std_logic;
signal bi : std_logic_vector((DataWidth-1) downto 0);



-- sinc3 filter
component FLT is
port(RESN, MOUT, MCLK, CNR : in std_logic;
                       CN5 : out std_logic_vector(4 downto 0)
);
end component;






begin
-- qui assegno i segnali al componente in esame
-- port map: component pin => testbench signal

dut: FLT port map (

RESN => reset,
MOUT => SDO,
MCLK => sck,
CNR => sck4,
CN5 => CN5


);




-- qui mi sembra io faccia partire dei processi concorrenti

stim_proc: process
begin        
   -- hold reset state at startup
     reset <= '0';
   wait for 1 ns;    
    reset <= '1';
   wait;
end process;











serialize_proc: process

variable b : integer := 0; -- contatore di bit, b7, b6, b5, ....
variable it : integer; -- contatore iterazioni


begin
-- inizializzo le variabili e i segnali
sck <= '0';
sck2 <= '0';
sck4 <= '0';
w <= '0';
a_slv <= (others => '0'); -- inizializzo tutto a 0  
    wait for 1 ns;


-- da adesso parte la simulazione vera e propria3

for it in 0 to 22 loop
b := (DataWidth); -- se io faccio partire b da 4, allora ho solo 4 passaggi nel ciclo while, se lo faccio partire da 5 allora ne ho 5

while (b>0) loop
bi <= std_logic_vector(to_unsigned(b-1, bi'length));
SDO <= a_slv(b-1);

wait for 10 ns;
sck <= not(sck);

if (sck = '1') then
b := b-1;
sck2 <= not(sck2);
if (sck2 = '1') then
sck4 <= not(sck4); -- sck4 period is 4 times sck period
end if;
end if;

end loop;

if (it < 20) then -- let's shift right to increase density of '1' in SDO signal
a_slv <= a_slv((DataWidth-2) downto 0) & '1';
end if;

if (it > 34) then -- let's shift left to decrease density of '1' in SDO signal
a_slv <= '0' & a_slv((DataWidth-1) downto 1) ;
end if;

w <= not(w); -- for debug purposes only

end loop;



wait;
end process;



end Behavioral;