This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/783085/ds90lv804-buffering-a-fpga-to-fpga-data-connection
我正在寻找一种解决方案来缓冲2个 FPGA 之间的5通道(4个数据通道+ 1个时钟) LVDS 链路。
LVDS 时钟约为74MHz；数据速率约为300Mbps。
是否可以将 DS90LV804用于数据线路、 将 DS90LV001用于 clk、 或者不同 的 IC 是否会产生过多的偏斜？
