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https://e2e.ti.com/support/interface-group/interface/f/interface-forum/678278/sn65hvd09-rs422-side_b-ttl-3-3level-io-side_a
多个 RS422信号将在 FPGA 中端接。
使用 SN65HVD09收发器、A 侧提供 TTL 输出、该输出将在 FPGA IO 引脚端接、这是一个5V 部件。
问题是我们是否需要在 A 侧使用电平转换器来实现所有 TTL 输出？？？ 连接 FPGA？ 。
FPGA IO 最大为3.3
Sathiyanathan
