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器件型号：MSP430FR2475 大家好！！
我正在尝试在 MSP430FR2475中使用两个 UART 通道、我已成功实现具有接收中断的 UART1 (115200波特率)、 但现在我正在尝试以相同的波特率实现具有接收中断的 UART0、但它不起作用。AM 遵循 UART1针对 UART0的相同程序、有什么问题？ 我已经提到下面的代码、请检查、如果您有解决方案、请提前通知我、谢谢。
int main(void)
{
Clock_Init();
GPIO_Init();
UART1_Init();
UART0_Init();
Software_Trim();
UCA0TXBUF =30;(Not Working)
while(!(UCA0IFG&UCTXIFG));
_delay_cycles(500);
UCA1TXBUF =20;(Working)
while(!(UCA1IFG&UCTXIFG));
_delay_cycles(500);
while(1)
{
}
}
#pragma vector=USCI_A1_VECTOR// Sensor ( Working UART)
__interrupt void USCI_A1_ISR(void)
{
UCA1IFG &=~ UCRXIFG;
rx_buffer[rx_ptr++] = UCA1RXBUF;
}
//UART master
#pragma vector=USCI_A0_VECTOR (Not Working UART)
__interrupt void USCI_A0_ISR(void)
{
UCA0IFG &=~ UCRXIFG;
m_rx_buffer[m_rx_ptr++] = UCA0RXBUF;
}
void GPIO_Init(void)
{
P3DIR |= BIT7;
P3DIR|= BIT5; //RX Encoder
P3DIR &= ~BIT7;
//P5DIR &= ~ BIT0;//Master enable
P2DIR |= BIT4;//LMS enable
P5DIR |= BIT0;//master enable
}
void UART0_Init()//Master
{
SYSCFG3 |= USCIA0RMP; //eUSCI_A port remap
P5SEL0 |= BIT1 | BIT2;
UCA0CTLW0 |= UCSWRST;
UCA0CTLW0 |= UCSSEL__SMCLK;
UCA0CTLW0 |= UCPEN_1 | UCPAR__EVEN;
UCA0BR0 = 4; // 9600 baud rate
UCA0BR1 = 0x00;
UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_5;
UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI
UCA0IE |= UCRXIE; // Enable USCI_A1 RX interrupt
__bis_SR_register(GIE);
}
void UART1_Init()//LMS OKAY
{
SYSCFG3 |= USCIA0RMP; //eUSCI_A port remap
P2SEL0 |= BIT5 | BIT6;
UCA1CTLW0 |= UCSWRST;
UCA1CTLW0 |= UCSSEL__SMCLK;
UCA1CTLW0 |= UCPEN_1 | UCPAR__EVEN;
UCA1BR0 = 4; // 8000000/16/115200
UCA1BR1 = 0x00;
UCA1MCTLW = 0x4900 | UCOS16 | UCBRF_5;
UCA1CTLW0 &= ~UCSWRST; // Initialize eUSCI
UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt
__bis_SR_register(GIE); // interrupts enabled
}
void Clock_Init(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
CSCTL1 = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_3;// DCOFTRIM=3, DCO Range = 8MHz
CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
Software_Trim(); // Software Trim to get the best DCOFTRIM value
PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings
}
void Software_Trim()
{
unsigned int oldDcoTap = 0xffff;
unsigned int newDcoTap = 0xffff;
unsigned int newDcoDelta = 0xffff;
unsigned int bestDcoDelta = 0xffff;
unsigned int csCtl0Copy = 0;
unsigned int csCtl1Copy = 0;
unsigned int csCtl0Read = 0;
unsigned int csCtl1Read = 0;
unsigned int dcoFreqTrim = 3;
unsigned char endLoop = 0;
do
{
CSCTL0 = 0x100; // DCO Tap = 256
do
{
CSCTL7 &= ~DCOFFG; // Clear DCO fault flag
}while (CSCTL7 & DCOFFG); // Test DCO fault flag
__delay_cycles((unsigned int)3000 * MCLK_FREQ_MHZ);// Wait FLL lock (FLLUNLOCK) to be stable
// Suggest to wait 24 cycles of divided FLL reference clock
while((CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)) && ((CSCTL7 & DCOFFG) == 0));
csCtl0Read = CSCTL0; // Read CSCTL0
csCtl1Read = CSCTL1; // Read CSCTL1
oldDcoTap = newDcoTap; // Record DCOTAP value of last time
newDcoTap = csCtl0Read & 0x01ff; // Get DCOTAP value of this time
dcoFreqTrim = (csCtl1Read & 0x0070)>>4;// Get DCOFTRIM value
if(newDcoTap < 256) // DCOTAP < 256
{
newDcoDelta = 256 - newDcoTap; // Delta value between DCPTAP and 256
if((oldDcoTap != 0xffff) && (oldDcoTap >= 256)) // DCOTAP cross 256
endLoop = 1; // Stop while loop
else
{
dcoFreqTrim--;
CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
}
}
else // DCOTAP >= 256
{
newDcoDelta = newDcoTap - 256; // Delta value between DCPTAP and 256
if(oldDcoTap < 256) // DCOTAP cross 256
endLoop = 1; // Stop while loop
else
{
dcoFreqTrim++;
CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
}
}
if(newDcoDelta < bestDcoDelta) // Record DCOTAP closest to 256
{
csCtl0Copy = csCtl0Read;
csCtl1Copy = csCtl1Read;
bestDcoDelta = newDcoDelta;
}
}while(endLoop == 0); // Poll until endLoop == 1
CSCTL0 = csCtl0Copy; // Reload locked DCOTAP
CSCTL1 = csCtl1Copy; // Reload locked DCOFTRIM
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
}
此致、
Aravinth K
