This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/588445/lm21212-2-is-the-low-side-fet-conducting-if-the-en-input-is-low
在未启用电源的情况下-由于 EN 引脚处于低电平或 Avin 低于其 UVLO 阈值-下 FET 导通并将 SW 输出内部连接至 GND、还是 SW 输出只是保持悬空？ 数据表未描述控制逻辑中发生的情况。
