工具/软件：
Champ、
我的客户将把 RGMII 2、RGMII 3 和 RGMII 4 用于 DRA821 上的三个以太网端口、因为只有两个 SERDES 和 PCIe、而 USB 则需要其中两个。
客户希望获得补丁来在 DRA821 EVM 上启用 RGMII 2、并以 GESI 板作为基准、以启用所有三个 RGMII 端口。
Br、Rich
您好 Rich、
我已启用 Linux 的 RGMII2 并能够与远程器件进行通信。
请查找以下日志和代码参考、以通过本地 Linux Diver 启用 RGMII。
k3-j7200-evm-quad-port-eth-exp.dtso 文件：
e2e.ti.com/.../k3_2D00_j7200_2D00_evm_2D00_quad_2D00_port_2D00_eth_2D00_exp.dtso
k3-j7200-common-proc-board.dts 文件： 
测试日志：
从您的参考中 Ping 测试日志 
注意：
由于 TI EVM 仅支持 RGMII2、因此高于 Dtso 仅配置 RGMII2 引脚、但用于参考为所有 CPSW 端口提供的配置信息。
此致、
Sudheer
您好 TI
我应用 RGMII 补丁。
来自 A72 RGMII 的 eth1 通过 ping 命令运行测试。 但 iperf 测试失败 
10/100 工作、但 1G 不工作。
你（们）好
修补程序。 但如果仍然以 1G 速度不工作。
我还有一个新问题：如何 在 uboot 中启用该 RGMII 端口？？？
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-moxa-uc-8600a.dts b/arch/arm64/boot/dts/ti/k3-j7200-moxa-uc-8600a.dts
index 7a3a9188c..d9bbe3ddc 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-moxa-uc-8600a.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-moxa-uc-8600a.dts
@@ -433,6 +433,7 @@
cpsw5g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
@@ -457,7 +458,7 @@
&cpsw0_port1 {
status = "disabled";
phy-handle = <&cpsw5g_phy1>;
- phy-mode = "rgmii-rxid";
+ phy-mode = "rgmii-id";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 1>;
};
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 81dd1c344..e4965439d 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -210,20 +210,29 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = {
static const
struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = {
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x0, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x4, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x8, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0xC, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x10, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x14, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x18, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x1C, 4, 4), },
};
static const
struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
+ .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
};
static const
@@ -231,6 +240,7 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
+ .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
.num_ports = 4,
.num_qsgmii_main_ports = 1,
};
@@ -240,6 +250,7 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
+ .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
.num_ports = 8,
.num_qsgmii_main_ports = 2,
};
@@ -251,6 +262,7 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
BIT(PHY_INTERFACE_MODE_USXGMII),
.num_ports = 8,
+ .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
.num_qsgmii_main_ports = 2,
};
你（们）好
[引述 userid=“540868" url="“ url="~“~/support/processors-group/processors/f/processors-forum/1501242/dra821u-linux-configuration-for-dra821u-with-gesi-rgmii2/5861011 #5861011“]你有没有这样的发现吗?
在调整 PHY 延迟后、我需要检查 1Gbps 的 iperf。
[/报价]我已经在 PHY 侧进行了延迟调整测试、并从 MAC 侧禁用了延迟、iprf 成功地以 1Gbps 运行。
更多信息、请参阅以下捕获内容。 
用于参考的器件树配置。 
此致、
Sudheer