主题中讨论的其他器件:AM62L、 SysConfig
工具/软件:
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工具/软件:
尊敬的:
1.tispl.bin 是否适用于 DDR?
是的、SDK 11.0.15.5 中提供的 TF-A 应该具有 DDR4 支持。
1.tispl.bin 是否适用于 DDR?
是的、tispl.bin 在 DDR 上运行。 如果未正确配置 DDR、tispl.bin 可能不会在控制台上打印任何消息。
3.如果我从 EVM 更改 DDR、我认为我需要重新调整 DDR 参数。 我是否应该将 SysConfig 输出的.dtsi 文件与 tf-A 结合使用?
是的、您应使用 SysConfig 工具生成新的 DDR 配置数据并将其集成到 TF-A
尊敬的 Bin:
感谢您的支持。
您应该使用 SysConfig 工具生成新的 DDR 配置数据并将其集成到 TF-A。
DDR 参数已进行调整并集成到 TF-A 中
但是、控制台在 BL1 停止、无法继续到 BL31。
控制台日志如下所示:
检查日志会显示输出了“bl1_platform_setup DDR init done“。
这是否意味着 DDR 参数正确?
如果 DDR 参数不正确且 BL31 无法引导、我应该如何处理此问题?
NOTICE: bl1_plat_arch_setup arch setup NOTICE: Booting Trusted Firmware NOTICE: BL1: v2.12.0(release):11.00.15-dirty NOTICE: BL1: Built : 12:24:23, May 29 2025 INFO: BL1: RAM 0x7080b000 - 0x7080f000 INFO: lpddr4_init <-- INFO: lpddr4 dtb: ctl-data ptr=0x7080618c, pi-data=0x70806834, phy-data=0x70806da4 NOTICE: BL1: dram_class: 10 INFO: memory node =0x28 INFO: lpddr4: probe done INFO: lpddr4/ddr4: init done INFO: start-status: offset =0x0 INFO: start-status reg: before =0x10460a00 INFO: Doing normal DDR initINFO: lpddr4: Start DDR controller INFO: lpddr4: start completed successfully status=0x0 INFO: start-status reg: after =0x10460a01 INFO: LPDDR4 start completed !! NOTICE: lpddr4: post start - PI training status=0x29c02000 INFO: lpddr4: post start - CTL Interrupt status=0x0 NOTICE: bl1_platform_setup DDR init done NOTICE: k3_bl1_handoff ENTERING WFI - end of bl1 01000000011a0000616d36326c00000000000000544553540000010000000100
尊敬的 Bin 和 JJD:
感谢您的支持。
我将提供以下有关 DDR4 的信息。
您能否检查 DDR 参数是否有任何问题?
* DDR 器件型号
MT40A512M16TD-062EAIT:R
*数据表和 sysconfig 文件
e2e.ti.com/.../4863.DDR4.zip
有一个问题值得关注。
分析 UART 引导控制台日志后、测试了器件类型。
这与 BL31 无法启动的问题无关、对吧?
----------------------- SoC ID Header Info: ----------------------- NumBlocks : [1] ----------------------- SoC ID Public ROM Info: ----------------------- SubBlockId : SubBlockSize : DeviceName : am62l DeviceType : TEST DMSC ROM Version : [0, 1, 0, 0] R5 ROM Version : [0, 1, 0, 0]
对于 DDR 配置、我们首先进行基本更改、然后根据需要进行优化。 是否可以尝试使用附加的配置进行引导:
/cfs-file/__key/communityserver-discussions-components-files/791/untitled-_2800_39_2900_.syscfg
它只会将密度变为 8Gb
此致、
James
尊敬的 JJJD:
感谢您检查并连接 DDR 参数。
我使用随附的.dtsi 文件确认了操作。
因此、BL31 已正确引导。 但是、U-Boot 启动失败。
您能告诉我可能的原因吗? 启动日志如下所示。
NOTICE: bl1_plat_arch_setup arch setup NOTICE: Booting Trusted Firmware NOTICE: BL1: v2.12.0(release):11.00.15-dirty NOTICE: BL1: Built : 12:24:23, May 29 2025 INFO: BL1: RAM 0x7080b000 - 0x7080f000 INFO: lpddr4_init <-- INFO: lpddr4 dtb: ctl-data ptr=0x7080618c, pi-data=0x70806834, phy-data=0x70806da4 NOTICE: BL1: dram_class: 10 INFO: memory node =0x28 INFO: lpddr4: probe done INFO: lpddr4/ddr4: init done INFO: start-status: offset =0x0 INFO: start-status reg: before =0x10460a00 INFO: Doing normal DDR initINFO: lpddr4: Start DDR controller INFO: lpddr4: start completed successfully status=0x0 INFO: start-status reg: after =0x10460a01 INFO: LPDDR4 start completed !! NOTICE: lpddr4: post start - PI training status=0x29c02000 INFO: lpddr4: post start - CTL Interrupt status=0x0 NOTICE: bl1_platform_setup DDR init done NOTICE: k3_bl1_handoff ENTERING WFI - end of bl1 NOTICE: BL31: v2.12.0(release):11.00.15-dirty NOTICE: BL31: Built : 12:24:23, May 29 2025 INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: Maximum SPI INTID supported: 991 ERROR: Timeout waiting for boot notification INFO: stub copy 0x707f0000 0x80041000 0x707f6528 INFO: A53 stub copy passed ERROR: Timeout waiting for receive ERROR: Message receive failed (-60) ERROR: Failed to get response (-60) ERROR: Transfer send failed (-60) ERROR: Unable to communicate with the control firmware (-60) ERROR: Failed to initialize SOC (-60) INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x82000000 INFO: SPSR = 0x3c9 ERROR: Agent 0 Protocol 0x10 Message 0x7: not supported U-Boot SPL 2025.01-00464-g1d6ba4a32cdd-dirty (May 29 2025 - 19:36:32 +0000) SPL initial stack usage: 1744 bytes Trying to boot from MMC2 ERROR: Agent 0 Protocol 0x10 Message 0x7: not supported U-Boot 2025.01-00464-g1d6ba4a32cdd-dirty (May 29 2025 - 19:36:32 +0000) SoC: AM62LX SR1.0 TEST Model: MY COMPANY MODEL DRAM: 1 GiB ERROR: Agent 0 Protocol 0x10 Message 0x7: not supported Core: 83 devices, 31 uclasses, devicetree: separate NAND: 512 MiB MMC: mmc@fa10000: 0, mmc@fa00000: 1 Loading Environment from nowhere... OK In: serial@2800000 Out: serial@2800000 Err: serial@2800000 "Synchronous Abort" handler, esr 0x96000010, far 0x0 elr: 0000000084003254 lr : 0000000084003254 (reloc) elr: 00000000bfe97254 lr : 00000000bfe97254 x0 : 0000000000000000 x1 : 00000000bffec000 x2 : 0000000000000065 x3 : 00000000bffadf98 x4 : 0000000000000000 x5 : 00000000bde863f0 x6 : 0000000000000021 x7 : 00000000bde8df60 x8 : 0000000000006bcc x9 : 00000000bde863e0 x10: 0000000000000000 x11: 00000000bde8b878 x12: 0000000000000000 x13: 0000000000000200 x14: 00000000bde667f0 x15: 00000000bde66688 x16: 00000000bfedc358 x17: 0000000000000000 x18: 00000000bde74df0 x19: 00000000bff7eb5e x20: 00000000bff7eb38 x21: 0000000000000000 x22: 00000000bffa7b28 x23: 000000003be94000 x24: 0000000000000008 x25: 0000000000000000 x26: 0000000082039271 x27: 0000000082039000 x28: 0000000082039259 x29: 00000000bde66700 Code: b9002be0 79005be0 aa1403e0 9401daa7 (39400002) Resetting CPU ... resetting ... INFO: PSCI Power Domain Map: INFO: Domain Node : Level 2, parent_node 4294967295, State ON (0x0) INFO: Domain Node : Level 1, parent_node 0, State ON (0x0) INFO: CPU Node : MPID 0x0, parent_node 1, State ON (0x0) INFO: CPU Node : MPID 0xffffffffffffffff, parent_node 1, State OFF (0x2)
此致、
最终目的