Other Parts Discussed in Thread: AM67A
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器件型号： AM67A
您好、
之前、我将设备树配置为使用 LVDS 单通道 LVDS-1、LVDS-2 和 DSI-0 启用三个屏幕。 我有 LVDS-1 和 DSI-0 的视频输出。 但是、我发现在 SDK11 上、使用此设置时、仍然无法在 LVDS-2 上获得时钟信号。 我按照指南操作并应用了移除配套面板的补丁。
当我特意配置配套面板时、我在 LVDS-2 屏幕上获得重复的输出、但如果没有配套面板、它不会输出任何内容、则禁用外设。
cat /sys/kernel/debug/clk/clk_summary | grep dss
clk:232:8 1 1 0 320000000 0 0 50000 Y 30220000.dss fck
clk:232:4 1 1 0 82552000 0 0 50000 Y 30220000.dss vp2
clock-divider-oldi-dss1 1 1 0 87100000 0 0 50000 Y 30220000.dss vp1
clk:186:6 1 1 0 320000000 0 0 50000 Y 30200000.dss fck
clk:186:2 0 0 0 300000000 0 0 50000 Y 30200000.dss vp2
clock-divider-oldi-dss0 1 1 0 87100000 0 0 50000 Y 30200000.dss vp1请注意 VP1 上的 oldi-DSS1。 此时钟配置正确、表明已启用、但引脚实际上并未切换。
有人能帮我调试外设尽管在 kmsprint 和 clk_summary 中显示正确但仍然无法输出的原因吗？
kmsprint --device /dev/dri/card2
Connector 0 (41) LVDS-2 (connected)
Encoder 0 (40) NONE
Crtc 0 (39) 1920x720@56.36 87.100 1920/53/54/53/? 720/8/7/8/? 56 (56.36) P|D
Plane 0 (32) fb-id: 55 (crtcs: 0 1) 0,0 1920x720 -> 0,0 1920x720 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
FB 55 1920x720 XR24
Connector 1 (52) DSI-1 (connected)
Encoder 1 (51) NONE
Crtc 1 (50) 1280x800@64.01 82.550 1280/100/32/100/- 800/20/3/30/- 64 (64.01) P|D
Plane 1 (43) fb-id: 58 (crtcs: 0 1) 0,0 1280x800 -> 0,0 1280x800 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
FB 58 1280x800 XR24
以下是器件树的重要部分：
...
panel0 {
compatible = "dlc,dlc1010gig";
rotation = <180>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lcd_in0: endpoint {
remote-endpoint = <&oldi0_dss0_out>;
};
};
};
};
panel1 {
compatible = "dlc,dlc1010gig";
rotation = <180>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lcd_in1: endpoint {
remote-endpoint = <&oldi1_dss1_out>;
};
};
};
};
...
&dss0 {
status = "okay";
};
&dss0_ports {
#address-cells = <1>;
#size-cells = <0>;
/* VP1: LVDS Output (OLDI TX 0) */
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dss0_dpi0_out0: endpoint@0 {
reg = <0>;
remote-endpoint = <&oldi0_dss0_in>;
};
};
};
&oldi0_dss0 {
status = "okay";
};
&oldi0_dss0_ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
oldi0_dss0_in: endpoint {
remote-endpoint = <&dss0_dpi0_out0>;
};
};
port@1 {
reg = <1>;
oldi0_dss0_out: endpoint {
remote-endpoint = <&lcd_in0>;
};
};
};
&oldi1_dss0 {
status = "disabled";
};
&dss1 {
status = "okay";
clocks = <&k3_clks 232 8>,
<&dss1_vp1_clk>,
<&k3_clks 232 4>;
clock-names = "fck", "vp1", "vp2";
assigned-clocks = <&k3_clks 235 7>, /* DEV_OLDI_TX_CORE1_OLDI_PLL_CLK */
<&k3_clks 241 0>, /* DSS1-VP0 */
<&k3_clks 240 0>; /* DSS1-VP1 */
assigned-clock-parents = <&k3_clks 235 9>, /* DEV_OLDI_TX_CORE1_OLDI_PLL_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK */
<&k3_clks 241 1>, /* PLL 18 OLDI */
<&k3_clks 240 2>; /* PLL 17 DSI */
};
&dss1_ports {
#address-cells = <1>;
#size-cells = <0>;
/* VP0: LVDS Output (OLDI TX 1) */
port@0 {
reg = <0>;
status = "okay";
dss1_dpi0_out: endpoint {
status = "okay";
remote-endpoint = <&oldi1_dss1_in>;
};
};
/* DSS1-VP1: DSI Output */
port@1 {
reg = <1>;
dss1_dpi1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
&oldi1_dss1 {
status = "okay";
};
&oldi1_dss1_ports {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
oldi1_dss1_in: endpoint {
status = "okay";
remote-endpoint = <&dss1_dpi0_out>;
};
};
port@1 {
reg = <1>;
status = "okay";
oldi1_dss1_out: endpoint {
status = "okay";
remote-endpoint = <&lcd_in1>;
};
};
};
&dphy_tx0 {
status = "okay";
};
