Other Parts Discussed in Thread: J784S4XEVM
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器件型号：J784S4XEVM
您好：
我正在处理 TDA4 工程、并尝试使用从主域 R5F 内核 (MCU2_0、MCU3_0、MCU4_0) 访问 DDR 中的共享存储器区域（高地址：0x900000000） 老鼠
而完全相同的逻辑则可以很好地运行 MCU1_0 （MCU 域）、我无法向上的目标地址写入数据 MCU2、MCU3 和 MCU4 。
【我的配置】
MPU 设置
{
/* Region 9 configuration: shared buffer */
.regionId = 9U,
.enable = 1U,
.baseAddr = 0x50000000,
.size = CSL_ARM_R5_MPU_REGION_SIZE_256MB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 1U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 1U,
.cacheable = (uint32_t)FALSE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
.memAttr = 0U,
}, 链接器设置
#define DDR_SHARED_BUFFER_START 0x50000000 /* MCU <> MPU Shared Memory */
#define DDR_SHARED_BUFFER_SIZE 0x10000000 /* 256MB */
...
MEMORY
{
...
DDR_SHARED_BUFFER (RWIX) : ORIGIN = DDR_SHARED_BUFFER_START LENGTH = DDR_SHARED_BUFFER_SIZE
}
#define __CORE_SHARED_SPACE DDR_SHARED_BUFFER
section
/* MCU <> MPU Shared DDR Buffer */
shared_data_buffer : {} align(8) > __CORE_SHARED_SPACE MCU 内核源设置
uint8_t shard_buffer[64] __attribute__ ((section ("shared_data_buffer"), aligned (8)));
void SetRAT()
{
uint32_t test_num = 0, offset = 0;
UART_printf("Initializing RAT ...");
#define BASE_ADDR (0x50000000)
#define PHY_ADDR_HI (0x00000009)
#define PHY_ADDR_LO (0x00000000)
#ifdef BUILD_MCU1_0
//(0x40F90000)
#define RAT_BASE CSL_MCU_R5FSS0_RAT_CFG_BASE
test_num = 0x01;
offset = 0;
#endif
#ifdef BUILD_MCU2_0
//(0xff90000UL)
#define RAT_BASE CSL_R5FSS0_RAT_CFG_BASE
test_num = 0x02;
offset = 4;
#endif
#ifdef BUILD_MCU3_0
//(0xff90000UL)
#define RAT_BASE CSL_R5FSS1_RAT_CFG_BASE
test_num = 0x03;
offset = 8;
#endif
#ifdef BUILD_MCU4_0
//(0xff90000UL)
#define RAT_BASE CSL_R5FSS2_RAT_CFG_BASE
test_num = 0x04;
offset = 12;
#endif
#define REGION_ID (0x0)
*(unsigned int *)(RAT_BASE + 0x40 + (REGION_ID*0x10)) = 0;
*(unsigned int *)(RAT_BASE + 0x44 + (REGION_ID*0x10)) = BASE_ADDR; //IN ADDRESS
*(unsigned int *)(RAT_BASE + 0x48 + (REGION_ID*0x10)) = PHY_ADDR_LO; //lower 32bits of the real physical address
*(unsigned int *)(RAT_BASE + 0x4C + (REGION_ID*0x10)) = PHY_ADDR_HI; //Upper 16 bits of the real physical address.
*(unsigned int *)(RAT_BASE + 0x40 + (REGION_ID*0x10)) = 0x8000001C; // bit[31:31] : enable bit[5:0] size (2^SIZE)
UART_printf( "done.\n");
memcpy(shard_buffer + offset, &test_num, sizeof(test_num));内核设备树
shared_memory_region: adc-shared-memory@900000000{
compatible = "shared-dma-pool";
reg = <0x9 0x00 0x00 0x10000000>;
no-map;
};
结果
root@j784s4-evm:~# devmem2 0x900000000
/dev/mem opened.
Memory mapped at address 0xffffb7693000.
Read at address 0x900000000 (0xffffb7693000): 0x00000001
root@j784s4-evm:~# devmem2 0x900000004
/dev/mem opened.
Memory mapped at address 0xffffb396c000.
Read at address 0x900000004 (0xffffb396c004): 0xFFFFFFFF
root@j784s4-evm:~# devmem2 0x900000008
/dev/mem opened.
Memory mapped at address 0xffffb56db000.
Read at address 0x900000008 (0xffffb56db008): 0xFFFFFFFF
root@j784s4-evm:~#
【问题】
1.查看 My RAT 配置：根据提供的代码片段（设置 BASE、PHY_ADDR_LO/HI、然后设置 CTRL 为 0x8000001C）、序列或用于主域 R5FSS 的位掩码中是否有任何逻辑错误？
2. 防火墙或 TISCI 要求：主域 R5F 内核 (MCU2/3/4) 是否专门需要防火墙或 TISCI 配置来访问或修改其自有的 RAT 寄存器（地址为 0x0FF90000）？
3、 域差异：MCU 域 (MCU1) 和主域 (MCU2/3/4) 之间的 RAT 初始化序列是否存在我应该了解的已知架构差异？
4、 Sciclient API 示例：能否提供一个具体示例、说明如何使用适用于主域 R5F 内核的 Sciclient API 正确打开 RAT 配置区域的防火墙？
谢谢你。
