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[参考译文] TDA4VH-Q1:如何在 TDA4 Linux 原生器件树中的同一 SERDES 下配置 USXGMII 和 SGMII?

Guru**** 2964790 points
请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1617294/tda4vh-q1-how-to-configure-both-usxgmii-and-sgmii-under-the-same-serdes-in-the-device-tree-for-tda4-linux-native

器件型号: TDA4VH-Q1

您好。
 Linux SDK9.2  
如何在器件树中的同一 SERDES 下为 TDA4 Linux 原生配置 USXGMII 和 SGMII?
SGMII 在 100MHz 上工作、而 USXGMII 在 156.25MHz 上工作。 在同一串行器/解串器下如何同时支持 SGMII 和 USXGMII?

在 SERDES2 上、lane2 和 lane3 配置为 USXGMII 并且已经正常工作(可以成功 ping)。 通道 1 配置为 SGMII。

当我启用 main_cpsw0_port6 (serdes2 lane1) 时、如下所示:
&main_cpsw0_port6 {
    status = "okay"; 
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_sgmii_link>;
    phy-names = "mac", "serdes";
    fixed-link {
        speed = <1000>;
        full-duplex;
    };
};
&serdes2 {
    status = "okay";
    #address-cells = <1>;
    #size-cells = <0>;

    serdes2_usxgmii_link: phy@2 {
        reg = <2>;
        cdns,num-lanes = <2>;
        #phy-cells = <0>;
        cdns,phy-type = <PHY_TYPE_USXGMII>;
        resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
    };
    serdes2_sgmii_link: phy@1 {
        reg = <1>;
        cdns,num-lanes = <1>;
        #phy-cells = <0>;
        cdns,phy-type = <PHY_TYPE_SGMII>;
        resets = <&serdes_wiz2 1>;
    };
};

我收到以下内核错误:

[ 2.521542] CDN-torrent-phy 5020000.serdes:等待 CMN 就绪超时

[2.528403] phy phy-5020000.serdes.14: phy poweron 失败-->–110

此致、

GJ




  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    您能否分享命令“k3conf dump clocks “的输出?

    此致、
    Tanmay

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你(们)好 Tanmay
    k3conf 转储时钟
      

    root@j784s4-evm:~# dmesg  | grep eth
    [    0.000000] psci: probing for conduit method from DT.
    [    1.034852] optee: probing for conduit method.
    [    1.457439] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
    [    1.470286] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
    [    1.477495] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
    [    1.487764] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
    [    1.497645] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
    [    2.373445] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
    [    2.386309] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
    [    2.393516] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
    [    2.403802] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
    [    2.413725] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
    [    2.421431] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
    [    2.547760] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110
    [    3.023202] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and con.
    root@j784s4-evm:~# k3conf dump clocks 406
    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Wed Mar 06 14:29:58 UTC 2024)              |
    | SoC    | J784S4 SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.0.6--v09.00.06 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |----------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                            | Status          | Clock Frequency |
    |----------------------------------------------------------------------------------------------------------------------------------|
    |   406     |     2    | DEV_SERDES_10G2_CLK                                                   | CLK_STATE_READY | 125000000       |
    |   406     |     3    | DEV_SERDES_10G2_CMN_REFCLK_M                                          | CLK_STATE_READY | 0               |
    |   406     |     3    | DEV_SERDES_10G2_CMN_REFCLK_M                                          | CLK_STATE_READY | 0               |
    |   406     |     4    | DEV_SERDES_10G2_CMN_REFCLK_P                                          | CLK_STATE_READY | 0               |
    |   406     |     5    | DEV_SERDES_10G2_CORE_REF1_CLK                                         | CLK_STATE_READY | 156250000       |
    |   406     |     6    | DEV_SERDES_10G2_CORE_REF_CLK                                          | CLK_STATE_READY | 156250000       |
    |   406     |     7    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
    |   406     |     8    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
    |   406     |     9    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000       |
    |   406     |    10    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
    |   406     |    12    | DEV_SERDES_10G2_IP1_LN0_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    13    | DEV_SERDES_10G2_IP1_LN0_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    14    | DEV_SERDES_10G2_IP1_LN0_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    15    | DEV_SERDES_10G2_IP1_LN0_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    16    | DEV_SERDES_10G2_IP1_LN0_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    17    | DEV_SERDES_10G2_IP1_LN0_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    18    | DEV_SERDES_10G2_IP1_LN1_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    19    | DEV_SERDES_10G2_IP1_LN1_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    20    | DEV_SERDES_10G2_IP1_LN1_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    21    | DEV_SERDES_10G2_IP1_LN1_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    22    | DEV_SERDES_10G2_IP1_LN1_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    23    | DEV_SERDES_10G2_IP1_LN1_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    24    | DEV_SERDES_10G2_IP1_LN2_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    25    | DEV_SERDES_10G2_IP1_LN2_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    26    | DEV_SERDES_10G2_IP1_LN2_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    27    | DEV_SERDES_10G2_IP1_LN2_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    28    | DEV_SERDES_10G2_IP1_LN2_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    29    | DEV_SERDES_10G2_IP1_LN2_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    30    | DEV_SERDES_10G2_IP1_LN3_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    31    | DEV_SERDES_10G2_IP1_LN3_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    32    | DEV_SERDES_10G2_IP1_LN3_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    33    | DEV_SERDES_10G2_IP1_LN3_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    34    | DEV_SERDES_10G2_IP1_LN3_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    35    | DEV_SERDES_10G2_IP1_LN3_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    48    | DEV_SERDES_10G2_IP2_LN2_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    49    | DEV_SERDES_10G2_IP2_LN2_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    50    | DEV_SERDES_10G2_IP2_LN2_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    51    | DEV_SERDES_10G2_IP2_LN2_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    52    | DEV_SERDES_10G2_IP2_LN2_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    53    | DEV_SERDES_10G2_IP2_LN2_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    54    | DEV_SERDES_10G2_IP2_LN3_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    55    | DEV_SERDES_10G2_IP2_LN3_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    56    | DEV_SERDES_10G2_IP2_LN3_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    57    | DEV_SERDES_10G2_IP2_LN3_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    58    | DEV_SERDES_10G2_IP2_LN3_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    59    | DEV_SERDES_10G2_IP2_LN3_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |   129    | DEV_SERDES_10G2_TAP_TCK                                               | CLK_STATE_READY | 0               |
    |----------------------------------------------------------------------------------------------------------------------------------|
    


    此致、

    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    根据时钟转储我可以看到 DEV_SERDES_10G2_CORE_REF_CLK 设置为 156250000。 它应该是 1000000。 为此、在 wiz 节点中、请将 assigned_clock_parent 设置为“10“、而不是“9“

    在 SerDes 节点中、您可以确保 PLL0 REFCLK 的时钟父级为 k3_clk 5 而不是 6。

    总体而言、SerDes 节点(除链路节点之外)应如下所示:

    	serdes_wiz2: wiz@5020000 {
    		compatible = "ti,j784s4-wiz-10g";
    		#address-cells = <1>;
    		#size-cells = <1>;
    		power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
    		clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
    		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
    		assigned-clocks = <&k3_clks 406 6>;
    		assigned-clock-parents = <&k3_clks 406 10>;
    		num-lanes = <4>;
    		#reset-cells = <1>;
    		#clock-cells = <1>;
    		ranges = <0x05020000 0x00 0x05020000 0x10000>;
    		status = "disabled";
    
    		serdes2: serdes@5020000 {
    			compatible = "ti,j721e-serdes-10g";
    			reg = <0x05020000 0x010000>;
    			reg-names = "torrent_phy";
    			resets = <&serdes_wiz2 0>;
    			reset-names = "torrent_reset";
    			clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
    				 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
    			clock-names = "refclk", "phy_en_refclk";
    			assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
    					  <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
    					  <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
    			assigned-clock-parents = <&k3_clks 406 5>,
    						 <&k3_clks 406 6>,
    						 <&k3_clks 406 6>;
    			#address-cells = <1>;
    			#size-cells = <0>;
    			#clock-cells = <1>;
    			status = "disabled";
    		};
    	};

    此致、
    Tanmay

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你好、Tanmay

    1.当 assigned-clock-parents 设置为 "10" 而不是 "9"时、 ethtool 的输出 eth1 显示链路为 10Gbps:

    root@j784s4-evm:~# ethtool eth1
    Settings for eth1:
            Supported ports: [ MII ]
            Supported link modes:   10000baseCR/Full
            Supported pause frame use: Symmetric Receive-only
            Supports auto-negotiation: Yes
            Supported FEC modes: Not reported
            Advertised link modes:  10000baseCR/Full
            Advertised pause frame use: Symmetric
            Advertised auto-negotiation: Yes
            Advertised FEC modes: Not reported
            Link partner advertised link modes:  10000baseCR/Full
            Link partner advertised pause frame use: No
            Link partner advertised auto-negotiation: No
            Link partner advertised FEC modes: Not reported
            Speed: 10000Mb/s
            Duplex: Full
            Auto-negotiation: on
            Port: MII
            PHYAD: 0
            Transceiver: internal
            Supports Wake-on: d
            Wake-on: d
            Current message level: 0x000020f7 (8439)
                                   drv probe link ifdown ifup rx_err tx_err hw
            Link detected: yes

    但是、它不能 ping 通。

    应用更改的相关器件树源代码片段 (assigned-clock-parents = <&k3_clks 406 10>;):
    serdes_wiz2: wiz@5020000 {
        compatible = "ti,j784s4-wiz-10g";
        #address-cells = <1>;
        #size-cells = <1>;
        power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
        clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
        clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
        
        /* The specific change: Parent clock index changed from 9 to 10 */
        assigned-clocks = <&k3_clks 406 6>;
        assigned-clock-parents = <&k3_clks 406 10>; 
        
        num-lanes = <4>;
        #reset-cells = <1>;
        #clock-cells = <1>;
        ranges = <0x05020000 0x00 0x05020000 0x10000>;
        status = "disabled";
    
        serdes2: serdes@5020000 {
            compatible = "ti,j721e-serdes-10g";
            reg = <0x05020000 0x010000>;
            reg-names = "torrent_phy";
            resets = <&serdes_wiz2 0>;
            reset-names = "torrent_reset";
            clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
                     <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
            clock-names = "refclk", "phy_en_refclk";
            assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
                              <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
                              <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
            assigned-clock-parents = <&k3_clks 406 5>,
                                     <&k3_clks 406 6>,
                                     <&k3_clks 406 6>;
            #address-cells = <1>;
            #size-cells = <0>;
            #clock-cells = <1>;
            status = "disabled";
        };
    };


    内核引导日志(错误观察)
    assigned-clock-parents = <&k3_clks 406 10>

    serdes2: serdes@5020000 {
       ...
       assigned-clock-parter =<&k3_CLKS 406 5>、
                      <&K3_CLKS 406 6>、
                      <&K3_CLKS 406 6>;
    ...
    }
    尽管链路 ethtool 在上一步中出现、但当此配置处于活动状态时、内核启动日志会指示在 PHY 初始化阶段失败:
    [    ...] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
    [    2.784010] cdns-torrent-phy 5020000.serdes: Timeout waiting for CMN ready
    [    2.790871] phy phy-5020000.serdes.14: phy poweron failed --> -110
    [    2.797500] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110

    root@j784s4-EVM:/proc/device-tree/bus@10000/wiz@5020000# hexdump assigned-clocks 0000000 0000 0f00 0000 9601 0000 0600 000000c root@j784s4-EVM:/proc/device-tree/bus@10000/wiz@5020000# hexdump assigned-clock-parents 0000000 0000 0f00 0000 9601 0000 0a00 000000c
    root@j784s4-evm:/proc/device-tree/bus@100000/wiz@5020000# hexdump assigned-clocks
    0000000 0000 0f00 0000 9601 0000 0600          
    000000c
    
    root@j784s4-evm:/proc/device-tree/bus@100000/wiz@5020000# hexdump assigned-clock-parents
    0000000 0000 0f00 0000 9601 0000 0a00          
    000000c

    root@j784s4-evm:~# k3conf dump clock 406
    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Wed Mar 06 14:29:58 UTC 2024)              |
    | SoC    | J784S4 SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.0.6--v09.00.06 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |----------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                            | Status          | Clock Frequency |
    |----------------------------------------------------------------------------------------------------------------------------------|
    |   406     |     2    | DEV_SERDES_10G2_CLK                                                   | CLK_STATE_READY | 125000000       |
    |   406     |     3    | DEV_SERDES_10G2_CMN_REFCLK_M                                          | CLK_STATE_READY | 0               |
    |   406     |     3    | DEV_SERDES_10G2_CMN_REFCLK_M                                          | CLK_STATE_READY | 0               |
    |   406     |     4    | DEV_SERDES_10G2_CMN_REFCLK_P                                          | CLK_STATE_READY | 0               |
    |   406     |     5    | DEV_SERDES_10G2_CORE_REF1_CLK                                         | CLK_STATE_READY | 156250000       |
    |   406     |     6    | DEV_SERDES_10G2_CORE_REF_CLK                                          | CLK_STATE_READY | 100000000       |
    |   406     |     7    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
    |   406     |     8    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
    |   406     |     9    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000       |
    |   406     |    10    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
    |   406     |    12    | DEV_SERDES_10G2_IP1_LN0_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    13    | DEV_SERDES_10G2_IP1_LN0_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    14    | DEV_SERDES_10G2_IP1_LN0_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    15    | DEV_SERDES_10G2_IP1_LN0_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    16    | DEV_SERDES_10G2_IP1_LN0_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    17    | DEV_SERDES_10G2_IP1_LN0_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    18    | DEV_SERDES_10G2_IP1_LN1_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    19    | DEV_SERDES_10G2_IP1_LN1_RXCLK                                         | CLK_STATE_READY | 0               |
    

    此致、
    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你好。Tanmay
      使用以下器件树配置时:

    &main_cpsw0 {
        status = "okay";
        pinctrl-names = "default";
    };
    
    &main_cpsw0_port1 {
        status = "okay";
        phy-mode = "usxgmii";
        mac-address = [00 00 00 00 00 00];
        phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
        phy-names = "mac", "serdes";
        fixed-link {
            speed = <10000>;
            full-duplex;
        };
    };
    
    &main_cpsw0_port2 {
        status = "okay";
        phy-mode = "usxgmii";
        mac-address = [00 00 00 00 00 00];
        phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
        phy-names = "mac", "serdes";
        fixed-link {
            speed = <10000>;
            full-duplex;
        };
    };
    
    &serdes_wiz2 {
        status = "okay";
        assigned-clock-parents = <&k3_clks 406 10>;
    };
    
    &serdes2 {
        status = "okay";
        #address-cells = <1>;
        #size-cells = <0>;
        assigned-clock-parents = <&k3_clks 406 5>,
                                 <&k3_clks 406 6>,
                                 <&k3_clks 406 6>;
    };

    USXGMII 连接成功(ping 使用以下 CPSW 配置):

    但是、当我 在中添加 serdes2_sgmii_link PHY 节点定义时 &serdes2 、如下所示:

       serdes2_sgmii_link:PHY@1{
          reg =<1>;
          CDN、num-lanes =<1>;
          #phy-cells =<0>;
          CDN、phy-type = ;
          RESET =<&SERDES_wiz2 1>;
       };


    &serdes2 {
        status = "okay";
        #address-cells = <1>;
        #size-cells = <0>;
        assigned-clock-parents = <&k3_clks 406 5>,
                     <&k3_clks 406 6>,
                     <&k3_clks 406 6>;
        serdes2_usxgmii_link: phy@2 {
            reg = <2>;
            cdns,num-lanes = <2>;
            #phy-cells = <0>;
            cdns,phy-type = <PHY_TYPE_USXGMII>;
            resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
        };
        serdes2_sgmii_link: phy@1 {
            reg = <1>;
            cdns,num-lanes = <1>;
            #phy-cells = <0>;
            cdns,phy-type = <PHY_TYPE_SGMII>;
            resets = <&serdes_wiz2 1>;
        };
    };


    系统出现故障、并出现以下错误:

        2.534484] CDN-torrent-phy 5020000.serdes:等待 CMN 就绪超时
    [2.541346]   phy phy-5020000.serdes.15: phy power on failed -->–110
    [2.547624]   am65-cpsw-nuss:c000000.ethernet 探测失败、错误为–110

    此致、
    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    SGMII 串行器/解串器节点的复位优先级错误。

    CDN、phy-type = ;
    - RESET =<&SERDES_wiz2 1>;
    + RESET =<&SERDES_wiz2 2>;

    对于串行器/解串器通道 1、应使用 2 作为复位通道编号。

    您能否通过上述更改进行检查、如果它  是否解决了开机故障问题?

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你好  Sudheer
    我已将配置修改为:

    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
    	assigned-clock-parents = <&k3_clks 406 5>,
    				 <&k3_clks 406 6>,
    				 <&k3_clks 406 6>;
    	serdes2_usxgmii_link: phy@2 {
    		reg = <2>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_USXGMII>;
    		resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
    	};
    
    	serdes2_sgmii_link: phy@1 {
    		reg = <1>;
    		cdns,num-lanes = <1>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_SGMII>;
    		resets = <&serdes_wiz2 2>;
    	};
    };

    但是、我仍然会遇到以下错误:

                   cdns-torrent-phy 5020000.serdes: Timeout waiting for CMN ready
    [    2.315223] phy phy-5020000.serdes.14: phy poweron failed --> -110
    [    2.321499] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110
    ```"

    此致、
    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    您能提供串行器/解串器通道控制节点信息。

    还要确认没有应用程序在使用 SerDes2 的任何其他内核上运行?

    此外、提供以下串行器/解串器寄存器转储。

    基本地址:0x05020000
    具有偏移地址的寄存器如下:

    串行器/解串器顶部 CTRL:0x408
    复位:0x40C
    PLL 锁定状态:0xE000
    LaneCTL0:0x480 +(通道编号* 0x40) 每个通道的偏移量
    Lane Div:0x484
    通道 Allign:0x488
    通道状态:0x48C

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你好 Sudheer

      

    #define USXGMII 1
    #define SGMII6 
    &main_cpsw0 {
    	status = "okay";
    	pinctrl-names = "default";
    };
    #if USXGMII	
    
     &main_cpsw0_port1 {
    	status = "okay"; //"okay"; //"okay";
    	phy-mode = "usxgmii";
    	mac-address = [00 00 00 00 00 00];
    	phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
    	phy-names = "mac", "serdes";
    	fixed-link {
    		speed = <10000>;
    		full-duplex;
    	};
    };
     
    &main_cpsw0_port2 {
    	status = "okay";
    	phy-mode = "usxgmii";
    	mac-address = [00 00 00 00 00 00];
    	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
    	phy-names = "mac", "serdes";
    	fixed-link {
    		speed = <10000>;
    		full-duplex;
    	};
    };
    #endif
    
    #if   SGMII6 //SGMII6
    &main_cpsw0_port6 {
    	status = "okay";// "disabled";// 
    	phy-mode = "sgmii";
    	mac-address = [00 00 00 00 00 00];
     	phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_sgmii_link>;
    	phy-names = "mac", "serdes"; 
    	fixed-link {
    		speed = <1000>;
    		full-duplex;
    	};
     
    }; 
    #endif
     
    &serdes_wiz2 {
    	status = "okay";
    	assigned-clock-parents = <&k3_clks 406 10>;
    };
    
    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
    #if USXGMII	
    	assigned-clock-parents = <&k3_clks 406 5>,
    				 <&k3_clks 406 6>,
    				 <&k3_clks 406 6>;
    	serdes2_usxgmii_link: phy@2 {
    		reg = <2>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_USXGMII>;
    		resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
    	};
    #endif
    #if SGMII6 //SGMII6
    	serdes2_sgmii_link: phy@1 {
    		reg = <1>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_SGMII>;
    		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
    	};
    #endif
    };
    
    &serdes_ln_ctrl {
    	idle-states = 
    		<J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
    		<J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_IP4_UNUSED>,
    		<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,
    		<J784S4_SERDES1_LANE2_PCIE2_LANE0>, <J784S4_SERDES1_LANE3_IP4_UNUSED>,
    		<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
    		<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
    		<J784S4_SERDES4_LANE0_IP3_UNUSED>, <J784S4_SERDES4_LANE1_IP3_UNUSED>,
    		<J784S4_SERDES4_LANE2_QSGMII_LANE7>, <J784S4_SERDES4_LANE3_QSGMII_LANE8>;
    };
    

       

    同时确认没有应用程序使用 SerDes2 从任何其他内核运行?

    我已经验证了 R5F DTB、并确认没有复制 SerDes2。 仅使用 USXGMII 时会成功建立链路、仅使用 SGMII 时也正常工作。


    Root@j784s4-EVM:~# devmem2 0x05020000 = 0x00007364
    root@j784s4-EVM:~# devmem2 0x05020408 = 0x18100000
    Root@j784s4-EVM:~# devmem2 0x0502040c = 0xB2800000

    Root@j784s4-EVM:~# devmem2 0x0502e000 = 0x00820050
    root@j784s4-EVM:~# devmem2 0x05020480 = 0x70000000
    Root@j784s4-EVM:~# devmem2 0x05020484 = 0x00000000
    Root@j784s4-EVM:~# devmem2 0x0502048c = 0x00000002


    root@j784s4-EVM:~# devmem2 0x050204c0 = 0x70800000
    root@j784s4-evm:~# devmem2 0x050204c4 = 0x00010002
    root@j784s4-evm:~# devmem2 0x050204c8 = 0x00000000
    Root@j784s4-EVM:~# devmem2 0x050204cc = 0x00000002


    root@j784s4-EVM:~# devmem2 0x05020500 = 0x713800C0
    root@j784s4-evm:~# devmem2 0x05020504 = 0x00010002
    Root@j784s4-EVM:~# devmem2 0x05020508 = 0x00000000
    root@j784s4-evm:~# devmem2 0x0502050c = 0x00000012


    root@j784s4-EVM:~# devmem2 0x05020540 = 0x713800C0
    root@j784s4-evm:~# devmem2 0x05020544 = 0x00010002
    root@j784s4-evm:~# devmem2 0x05020548 = 0x00000000
    root@j784s4-evm:~# devmem2 0x0502054c = 0x00000012

     

    此致、

    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    从串行器/解串器寄存器转储、仅锁定 PLL1、而不是 PLL0、因此我们观察到上述问题。

    您能否确认仅使用相同的串行器/解串器时钟配置 USXGMII/SGMII 是否正常工作? 还是您使用了默认的时钟配置?


    您还可以检查一次以下时钟映射。

    assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
        <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
        <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
    assigned-clock-parents = <&k3_clks 406 5>,
        <&k3_clks 406 6>,
        <&k3_clks 406 5>;


    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你(们)好 Sudheer

    您能否确认、使用相同的串行器/解串器时钟配置 USXGMII/SGMII 是否正常工作? 还是您使用了默认时钟配置?

    这种配置使 USXGMII 能够正常工作。

    &main_cpsw0 {
    	status = "okay";
    	pinctrl-names = "default";
    };
    
     &main_cpsw0_port1 {
    	status = "okay"; //"okay"; //"okay";
    	phy-mode = "usxgmii";
    	mac-address = [00 00 00 00 00 00];
    	phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
    	phy-names = "mac", "serdes";
    	fixed-link {
    		speed = <10000>;
    		full-duplex;
    	};
    };
    
    &main_cpsw0_port2 {
    	status = "okay";
    	phy-mode = "usxgmii";
    	mac-address = [00 00 00 00 00 00];
    	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
    	phy-names = "mac", "serdes";
    	fixed-link {
    		speed = <10000>;
    		full-duplex;
    	};
    };
    
    
    
    &serdes_wiz2 {
    	status = "okay";
    	assigned-clock-parents = <&k3_clks 406 10>;
    };
    
    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
    	
         assigned-clock-parents = <&k3_clks 406 5>,
        <&k3_clks 406 6>,
        <&k3_clks 406 5>;   //   <&k3_clks 406 6>;   is ok
    	serdes2_usxgmii_link: phy@2 {
    		reg = <2>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_USXGMII>;
    		resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
    	};
    
    };
    



    此配置启用 SGMII  即为链路建立。
    &main_cpsw0 {
    	status = "okay";
    	pinctrl-names = "default";
    };
    
    
    &main_cpsw0_port6 {
    	status = "okay";// "disabled";// 
    	phy-mode = "sgmii";
    	mac-address = [00 00 00 00 00 00];
     	phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_sgmii_link>;
    	phy-names = "mac", "serdes";
    	
    	fixed-link {
    		speed = <1000>;
    		full-duplex;
    	};
    
    }; 
    
     
    &serdes_wiz2 {
    	status = "okay";
    	assigned-clock-parents = <&k3_clks 406 10>;
    };
    
    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
    
    	serdes2_sgmii_link: phy@1 {
    		reg = <1>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_SGMII>;
    		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
    	};
    };
    

     

    您是否还能检查以下时钟映射一次

    我检查了一下。

    serdes_wiz2: wiz@5020000 {
    		compatible = "ti,j784s4-wiz-10g";
    		#address-cells = <1>;
    		#size-cells = <1>;
    		power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
    		clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
    		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
    		assigned-clocks = <&k3_clks 406 6>;
    		assigned-clock-parents = <&k3_clks 406 10>;
    		num-lanes = <4>;
    		#reset-cells = <1>;
    		#clock-cells = <1>;
    		ranges = <0x05020000 0x00 0x05020000 0x10000>;
    
    		status = "disabled";
    
    		serdes2: serdes@5020000 {
    			compatible = "ti,j721e-serdes-10g";
    			reg = <0x05020000 0x010000>;
    			reg-names = "torrent_phy";
    			resets = <&serdes_wiz2 0>;
    			reset-names = "torrent_reset";
    			clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
    				 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
    			clock-names = "refclk", "phy_en_refclk";
    			assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
    					  <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
    					  <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
    			assigned-clock-parents = <&k3_clks 406 6>,
    						 <&k3_clks 406 6>,
    						 <&k3_clks 406 6>;
    			#address-cells = <1>;
    			#size-cells = <0>;
    			#clock-cells = <1>;
    
    			status = "disabled";
    		};
    	};



    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
    	
    	assigned-clock-parents = <&k3_clks 406 5>,
        <&k3_clks 406 6>,
        <&k3_clks 406 5>;
        
    }    
    
    or
    
    
    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
    	
    	assigned-clock-parents = <&k3_clks 406 5>,
        <&k3_clks 406 6>,
        <&k3_clks 406 6>;
        
    }  
    

    我无法将 USXGMII 和 SGMII 与上述配置同时使用。

    此致、

    GJ





  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    感谢您分享 SGMII 和 USXGMII 工作配置的详细信息。

    您能确认一下、侧的串行器/解串器 ln_ctrl 与以下内容相同。

    SDK 中的默认值:
     

    serdes_ln_ctrl: mux-controller@4080 {
    compatible = "mmio-mux";
    reg = <0x00004080 0x30>;
    #mux-control-cells = <1>;
    mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
    <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
    <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
    <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
    <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
    <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
    };


    如果与上述相同、默认 SDK 中将出现问题、则不会为 SerDes4 配置通道控制。

    实际节点应如下所示(正确的节点):
    serdes_ln_ctrl: mux-controller@4080 {
    compatible = "mmio-mux";
    reg = <0x00004080 0x50>;
    #mux-control-cells = <1>;
    mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
    <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
    <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
    <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
    <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
    <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
    <0x40c0 0x3>, <0x40c4 0x3>, /* SERDES4 lane0/1 select */
    <0x40c8 0x3>, <0x40cc 0x3>; /* SERDES4 lane2/3 select */
    };
    


    如果您的一方与上述情况不同、您能否通过使用上述配置进行检查。

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你(们)好 Sudheer
      
    我应用了下面的更新、但错误仍然存在

                    serdes_ln_ctrl: mux-controller@4080 {
                            compatible = "mmio-mux";
    -                       reg = <0x00004080 0x30>;
    +                       reg = <0x00004080 0x50>;
                            #mux-control-cells = <1>;
                            mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
                                            <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
                                            <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
                                            <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
                                            <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
    -                                       <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
    +                                       <0x40a8 0x3>, <0x40ac 0x3>, /* SERDES2 lane2/3 select */
    +                                       <0x40c0 0x3>, <0x40c4 0x3>, /* SERDES4 lane0/1 select */
    +                                       <0x40c8 0x3>, <0x40cc 0x3>; /* SERDES4 lane2/3 select */
                    };

    日志:
    [ 2.316591] CDNs-torrent-phy 5020000.serdes:等待 CMN 就绪超时
    [2.32353] phy phy-5020000.serdes.14: phy power on failed -->–110
    [2.329723] am65-cpsw-Nuss:c000000.Ethernet 探测失败、错误为–110

    此致、

    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、  

    您能否共享 CTRL MMR 寄存器组中的串行器/解串器通道控制寄存器。  

    此外、使用 k3conf 共享 SerDes 时钟转储。  

    此致、  

    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你(们)好
     
    CTRL MMR 寄存器(端口 1、端口 2、角色 6)和串行器/解串器时钟转储

    root@j784s4-evm:~# devmem2 0x00104044 
    /dev/mem opened.
    Memory mapped at address 0xffff8781c000.
    Read at address  0x00104044 (0xffff8781c044): 0x00000002
    root@j784s4-evm:~# devmem2 0x00104048 
    /dev/mem opened.
    Memory mapped at address 0xffff92883000.
    Read at address  0x00104048 (0xffff92883048): 0x00000002
    root@j784s4-evm:~# devmem2 0x00104058  
    /dev/mem opened.
    Memory mapped at address 0xffffae5a7000.
    Read at address  0x00104058 (0xffffae5a7058): 0x00000003
    root@j784s4-evm:~# 
    root@j784s4-evm:~# km
    kmod           kmsblank       kmsprint       kmstest        kmstest.kms++  
    root@j784s4-evm:~# k 
    k3conf           kbd_mode         kbdinfo          kbdrate          kill             kill.util-linux  killall          kmod             kmsblank         kmsprint         kmstest          kmstest.kms++
    root@j784s4-evm:~# k3conf  dump clock  406
    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version 0.3-nogit built Wed Mar 06 14:29:58 UTC 2024)              |
    | SoC    | J784S4 SR1.0                                                        |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.0.6--v09.00.06 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |----------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                            | Status          | Clock Frequency |
    |----------------------------------------------------------------------------------------------------------------------------------|
    |   406     |     2    | DEV_SERDES_10G2_CLK                                                   | CLK_STATE_READY | 125000000       |
    |   406     |     3    | DEV_SERDES_10G2_CMN_REFCLK_M                                          | CLK_STATE_READY | 0               |
    |   406     |     3    | DEV_SERDES_10G2_CMN_REFCLK_M                                          | CLK_STATE_READY | 0               |
    |   406     |     4    | DEV_SERDES_10G2_CMN_REFCLK_P                                          | CLK_STATE_READY | 0               |
    |   406     |     5    | DEV_SERDES_10G2_CORE_REF1_CLK                                         | CLK_STATE_READY | 156250000       |
    |   406     |     6    | DEV_SERDES_10G2_CORE_REF_CLK                                          | CLK_STATE_READY | 100000000       |
    |   406     |     7    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
    |   406     |     8    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
    |   406     |     9    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000       |
    |   406     |    10    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
    |   406     |    12    | DEV_SERDES_10G2_IP1_LN0_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    13    | DEV_SERDES_10G2_IP1_LN0_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    14    | DEV_SERDES_10G2_IP1_LN0_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    15    | DEV_SERDES_10G2_IP1_LN0_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    16    | DEV_SERDES_10G2_IP1_LN0_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    17    | DEV_SERDES_10G2_IP1_LN0_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    18    | DEV_SERDES_10G2_IP1_LN1_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    19    | DEV_SERDES_10G2_IP1_LN1_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    20    | DEV_SERDES_10G2_IP1_LN1_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    21    | DEV_SERDES_10G2_IP1_LN1_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    22    | DEV_SERDES_10G2_IP1_LN1_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    23    | DEV_SERDES_10G2_IP1_LN1_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    24    | DEV_SERDES_10G2_IP1_LN2_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    25    | DEV_SERDES_10G2_IP1_LN2_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    26    | DEV_SERDES_10G2_IP1_LN2_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    27    | DEV_SERDES_10G2_IP1_LN2_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    28    | DEV_SERDES_10G2_IP1_LN2_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    29    | DEV_SERDES_10G2_IP1_LN2_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    30    | DEV_SERDES_10G2_IP1_LN3_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    31    | DEV_SERDES_10G2_IP1_LN3_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    32    | DEV_SERDES_10G2_IP1_LN3_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    33    | DEV_SERDES_10G2_IP1_LN3_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    34    | DEV_SERDES_10G2_IP1_LN3_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    35    | DEV_SERDES_10G2_IP1_LN3_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    48    | DEV_SERDES_10G2_IP2_LN2_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    49    | DEV_SERDES_10G2_IP2_LN2_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    50    | DEV_SERDES_10G2_IP2_LN2_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    51    | DEV_SERDES_10G2_IP2_LN2_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    52    | DEV_SERDES_10G2_IP2_LN2_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    53    | DEV_SERDES_10G2_IP2_LN2_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    54    | DEV_SERDES_10G2_IP2_LN3_REFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    55    | DEV_SERDES_10G2_IP2_LN3_RXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    56    | DEV_SERDES_10G2_IP2_LN3_RXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    57    | DEV_SERDES_10G2_IP2_LN3_TXCLK                                         | CLK_STATE_READY | 0               |
    |   406     |    58    | DEV_SERDES_10G2_IP2_LN3_TXFCLK                                        | CLK_STATE_READY | 0               |
    |   406     |    59    | DEV_SERDES_10G2_IP2_LN3_TXMCLK                                        | CLK_STATE_READY | 0               |
    |   406     |   129    | DEV_SERDES_10G2_TAP_TCK                                               | CLK_STATE_READY | 0               |
    |----------------------------------------------------------------------------------------------------------------------------------|
    

    此致、

    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    CTRL MMR 寄存器(处理器 1、端口 2、角色 6)和串行器/解串器时钟转储

    我询问 SerDes 通道控制的 CTRL MMR 寄存器。
    0x001040c0
    0x001040c4
    0x001040c8
    0x001040cc


    串行器/解串器时钟转储似乎正常。

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你(们)好

      USXGMII 和 SGMII 使用 SerDes2。
      

    root@j784s4-evm:~# devmem2 0x1040a0
    /dev/mem opened.
    Memory mapped at address 0xffffb725e000.
    Read at address  0x001040A0 (0xffffb725e0a0): 0x00000000
    root@j784s4-evm:~# devmem2 0x1040a4
    /dev/mem opened.
    Memory mapped at address 0xffffa6886000.
    Read at address  0x001040A4 (0xffffa68860a4): 0x00000000
    root@j784s4-evm:~# devmem2 0x1040a8
    /dev/mem opened.
    Memory mapped at address 0xffff8283f000.
    Read at address  0x001040A8 (0xffff8283f0a8): 0x00000000
    root@j784s4-evm:~# devmem2 0x1040ac
    /dev/mem opened.
    Memory mapped at address 0xffffa4f9d000.
    Read at address  0x001040AC (0xffffa4f9d0ac): 0x00000000
    root@j784s4-evm:~# 


      服务器 4:
    root@j784s4-evm:~# devmem2 0x1040c0                                                                                                                      
    /dev/mem opened.                                                                                                                                         
    Memory mapped at address 0xffff8d9ab000.                                                                                                                 
    Read at address  0x001040C0 (0xffff8d9ab0c0): 0x00000000                                                                                                 
    root@j784s4-evm:~# devmem2 0x1040c4                                                                                                                      
    /dev/mem opened.                                                                                                                                         
    Memory mapped at address 0xffff80535000.                                                                                                                 
    Read at address  0x001040C4 (0xffff805350c4): 0x00000000                                                                                                 
    root@j784s4-evm:~# devmem2 0x1040c8                                                                                                                      
    /dev/mem opened.                                                                                                                                         
    Memory mapped at address 0xffffbc865000.                                                                                                                 
    Read at address  0x001040C8 (0xffffbc8650c8): 0x00000000                                                                                                 
    root@j784s4-evm:~# devmem2 0x1040cc                                                                                                                      
    /dev/mem opened.                                                                                                                                         
    Memory mapped at address 0xffff8c676000.                                                                                                                 
    Read at address  0x001040CC (0xffff8c6760cc): 0x00000000  

    此致、

    GJ



  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    了解您将使用 SerDes2 进行多链路连接。

    根据串行器/解串器通道映射、对于 USXGMII、通道 2 和通道 3 应为 1、但如上所示、寄存器转储为 0。



    请检查 一次串行器/解串器通道配置。

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你(们)好
     我观察到一个相互矛盾的现象:虽然我可以在仅启用两个 USXGMII 端口 (MAIN_Cpsw0_port1 和 MAIN_Cpsw0_port2) 的情况下成功 ping 通、但用于串行器/解串器通道控制的 CTRL MMR 寄存器仍读回为 0。


    为什么即使寄存器读数为 0、我仍然可以成功 ping?

    此致、

    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    由于您是 CPSW MAC 端口 1 和 MAC 端口 2 提供 USXGMII 支持的 SerDes2、因此应按照如下所示使用串行器/解串器通道映射。


    [quote userid=“464063“ url=“~/support/processors-group/processors/f/processors-forum/1617294/tda4vh-q1-how-to-configure-both-usxgmii-and-sgmii-under-the-same-serdes-in-the-device-tree-for-tda4-linux-native/6292580

    为什么即使寄存器读数为 0、我仍然可以成功 ping?

    [/报价]

    您能否使用正确的地址 (0x01040a0) 进行检查?


    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你(们)好
       在 CTRL MMR 寄存器中启用 SerDes2 Lane1(主角 6)和 Lane2/Lane3 (usxgmii) 后、读回的值现在与预期结果相匹配、如下所示:


    此致、

    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    对于上述内容、您是否仍然看到 PHY 上电问题?  

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你(们)好
      是的  

     [ 2.403733] CDN - torrent-phy 5020000.serdes:等待 CMN 就绪超时
    [2.410598] phy phy-5020000.serdes.14: phy poweron failed -->–110
    [2.416864] am65-cpsw-Nuss:c000000.ethernet 探测失败、错误为–110

    此致、

    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    让 我在下周初检查一下我们的一面、然后回到您的身边。

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你(们)好 Sudheer


       本周您是否有时间更新此问题?

    此致、

    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    很抱歉耽误你的时间。

    您能否请使用以下 SerDes 配置进行检查、并根据下面的更新 SerDes2、并根据您的要求进行静置。

    &serdes_wiz2 {
        assigned-clocks = <&k3_clks 407 6>, <&k3_clks 407 5>;
        assigned-clock-parents = <&k3_clks 407 10> /* Use 100MHz clock for SGMII */, <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
        status = "okay";
    };
    
    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
     
        assigned-clock-parents = <&k3_clks 406 6>,
    				 <&k3_clks 406 5>,
    				 <&k3_clks 406 6>;
    
    	serdes2_usxgmii12_link: phy@2 {
    		reg = <2>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_USXGMII>;
    		resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
    	};
    
    	serdes2_sgmii56_link: phy@0 {
    		reg = <0>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_SGMII>;
    		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
    	};
    };
    
    &serdes_ln_ctrl {
    	idle-states = 
    		<J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
    		<J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_IP4_UNUSED>,
    		<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,
    		<J784S4_SERDES1_LANE2_PCIE2_LANE0>, <J784S4_SERDES1_LANE3_IP4_UNUSED>,
    		<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
    		<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
    		<J784S4_SERDES4_LANE0_IP3_UNUSED>, <J784S4_SERDES4_LANE1_IP3_UNUSED>,
    		<J784S4_SERDES4_LANE2_QSGMII_LANE7>, <J784S4_SERDES4_LANE3_QSGMII_LANE8>;
    };


    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你好、Sudherr
       

    &serdes_wiz2 {
        assigned-clocks = <&k3_clks 407 6>, <&k3_clks 407 5>;
        assigned-clock-parents = <&k3_clks 407 10> /* Use 100MHz clock for SGMII */, <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
        status = "okay";
    };
    
    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
     
        assigned-clock-parents = <&k3_clks 406 6>,
    				 <&k3_clks 406 5>,
    				 <&k3_clks 406 6>;
    
    	serdes2_usxgmii12_link: phy@2 {
    		reg = <2>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_USXGMII>;
    		resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
    	};
    
    	serdes2_sgmii56_link: phy@0 {
    		reg = <0>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_SGMII>;
    		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
    	};
    };
    
    &serdes_ln_ctrl {
    	idle-states = 
    		<J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
    		<J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_IP4_UNUSED>,
    		<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,
    		<J784S4_SERDES1_LANE2_PCIE2_LANE0>, <J784S4_SERDES1_LANE3_IP4_UNUSED>,
    		<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
    		<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
    		<J784S4_SERDES4_LANE0_IP3_UNUSED>, <J784S4_SERDES4_LANE1_IP3_UNUSED>,
    		<J784S4_SERDES4_LANE2_QSGMII_LANE7>, <J784S4_SERDES4_LANE3_QSGMII_LANE8>;
    };
      

    使用此命令时可能会出现错误:
    [ 2.724329] hwmon hwmon2:TEMP1_INPUT 未连接到任何热区
    [ 2.735485] davinci_mdio c000f00.mdio:phy[3]:器件 c000f00.mdio:03、驱动程序 Marvell 88Q2112
    [2.761019] am65-cpsw-nuss c000000.ethernet:正在初始化 am65 cpsw Nuss 版本 0x6BA03102、cpsw 版本 0x6BA82902 端口:9 quirk0
    [ 2.874191] CDNs-torrent-phy 5020000.serdes:等待 CMN 就绪超时
    [2.881053] phy phy-5020000.serdes.14: phy power on failed -->–110
    [2.887679] am65-cpsw-nuss:c000000.ethernet 探测失败、错误为–110

    此致、

    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    抱歉、上面的器件树配置出错、我在时钟映射中给出了错误的器件 ID。

    请通过以下配置进行检查。

    &serdes_wiz2 {
        assigned-clocks = <&k3_clks 406 6>, <&k3_clks 406 5>;
        assigned-clock-parents = <&k3_clks 406 10> /* Use 100MHz clock for SGMII */, <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
        status = "okay";
    };
    
    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
     
        assigned-clock-parents = <&k3_clks 406 6>,
    				 <&k3_clks 406 5>,
    				 <&k3_clks 406 6>;
    
    	serdes2_usxgmii12_link: phy@2 {
    		reg = <2>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_USXGMII>;
    		resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
    	};
    
    	serdes2_sgmii56_link: phy@0 {
    		reg = <0>;
    		cdns,num-lanes = <2>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_SGMII>;
    		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
    	};
    };
    
    &serdes_ln_ctrl {
    	idle-states = 
    		<J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
    		<J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_IP4_UNUSED>,
    		<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,
    		<J784S4_SERDES1_LANE2_PCIE2_LANE0>, <J784S4_SERDES1_LANE3_IP4_UNUSED>,
    		<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
    		<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
    		<J784S4_SERDES4_LANE0_IP3_UNUSED>, <J784S4_SERDES4_LANE1_IP3_UNUSED>,
    		<J784S4_SERDES4_LANE2_QSGMII_LANE7>, <J784S4_SERDES4_LANE3_QSGMII_LANE8>;
    };


    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    从 CPSW SGMII 寄存器中、MAC 端口 4 已建立链路。

    您能否在下面添加 突出的更改并进行一次检查。


    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    让我在内部检查一次、然后返回给您。

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    嗨、 Sudheer


       得到了、感谢您的确认。

      我会等待您的内部审核结果、您可以在准备好后随时更新我。

    此致
    GJ

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    我将等待您的内部审核结果、请随时在准备好后更新我。

    当然、在进行内部验证后、我会告诉您一次。

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。
    你好 Sudheer,
        感谢您的更新。 能否在本周结束前得到答复?
    此致
    GJ
  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    我们尚未在外部进行任何验证、将在下周初更新您。

    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。
    你好 Sudheer,
         希望您做得好。 我只是检查一下你是否有任何进展。
    谢谢、
    GJ
  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    抱歉耽误您的时间、我们正在处理一些高优先级问题。
    我们的同事 Tanmay 正在   最后验证这一点 请等待他的答复。


    此致、
    Sudheer

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你好、Tanmay

    希望您做得好。 我只是检查一下你是否有任何进展。
    谢谢、
    GJ
  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、

    很抱歉耽误你的时间、

    您可以查看下面串行器/解串器节点中的重要变化。



    此致、
    Sudheer