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https://e2e.ti.com/support/processors-group/processors/f/processors-forum/565608/am3359-slew-rate-of-mdio_clk
尊敬的所有人：
MDIO_CLK 信号存在布局问题。 IO 驱动器的高压摆率会导致反射、因此、一些 PHY 正在检测双时钟边沿。 是否可以通过寄存器设置来降低此 IO 引脚(引脚 M18、ZCZ 封装)的压摆率/驱动强度？
此致
重做
