[参考译文] TDA4VH-Q1：Autosar Boot A72双核失败

您好！

您使用的是哪家 AUTOSAR 供应商？ 供应商是否在 TDA4VH 上测试了他们的堆栈并正在工作？

此外、这是 A72上的经典 AUTOSAR 堆栈还是这种某种形式的自适应 AUTOSAR？

我们通常见过适用于 MCU R5F 的 AUTOSAR 解决方案、但尚未适用于 A72。

您能否共享完整的 SBL 引导日志、包括发生的初始存储器加载？

此致、

Erick

我们使用本地公司 AUTOSAR。

他们也发现了问题,他们不知道如何解决。

我们使用 MCUR5 AUTOSAR 引导 A72进行测试。我已上传 ld 文件和启动代码。

SBL 从本地公司 AUTOSAR 加载整个映像不删除。启动 A72代码在不分类的启动代码中,它不在主函数中运行,我们确保它是不分类代码或编译器的问题。

STACK_SIZE = 0x00004000;
Mode_SYS_Stack_Size = 8192;
Mode_EXE_Stack_Size = 1024;
Mode_SVC_Stack_Size = 1024;
Mode_IRQ_Stack_Size = 1024;
Mode_FIQ_Stack_Size = 1024;
OSEE_HEAP_SIZE = 8096;
ENTRY(_start)
MEMORY
{
    ATCM (RWX) : ORIGIN = 0x00000000, LENGTH = 0x00007FFF
    BTCM (RWX) : ORIGIN = 0x41010000, LENGTH = 0x00007FFF
    OCMC_RAM (RWX) : ORIGIN = 0x41C82000, LENGTH = 0x7DA00
    MSMC_CODE (RWX) : ORIGIN = 0x70040000, LENGTH = 0x000C0000
    MSMC_DATA (RWX) : ORIGIN = 0x70300000, LENGTH = 0x000FFFFF
    DDR0_MCU_R5F (RWX) : ORIGIN = 0xA0500000, LENGTH = 0x007FFFFF
    DDR0_VECTORS (RWX) : ORIGIN = 0xFFFF0000, LENGTH = 0x00010000
}
SECTIONS
{
    .vectors 0x00000000 : {
        . = ALIGN(64);
        osee_vector_start = .;
        KEEP(*(.vectors))
        osee_vector_end = .;
    } > ATCM

    msmc_code_start_align (NOLOAD) : {
        . = ALIGN(osee_msmc_code_size_to_align);
        osee_msmc_code_start = .;
    } > OCMC_RAM

    .startup : {
        *(.startup)
        *(osee_boot_kernel_text)
    } > OCMC_RAM

    msmc_code_stop_align (NOLOAD) : {
        osee_msmc_code_stop = .;
        osee_msmc_code_log2ceil_size = ((osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 5) ? 5 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 6) ? 6 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 7) ? 7 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 8) ? 8 :(osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 9) ? 9 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 10) ? 10 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 11) ? 11 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 12) ? 12 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 13) ? 13 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 14) ? 14 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 15) ? 15 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 16) ? 16 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 17) ? 17 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 18) ? 18 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 19) ? 19 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 20) ? 20 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 21) ? 21 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 22) ? 22 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 23) ? 23 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 24) ? 24 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 25) ? 25 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 26) ? 26 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 27) ? 27 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 28) ? 28 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 29) ? 29 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 30) ? 30 : (osee_msmc_code_stop - osee_msmc_code_start) <= (1 << 31) ? 31 : -1);
        osee_msmc_code_size_to_align = 1 << osee_msmc_code_log2ceil_size;
        . = ALIGN(osee_msmc_code_size_to_align);
        osee_msmc_code_end = .;
    } > OCMC_RAM    

    msmc_data_start_align (NOLOAD) : {
        . = ALIGN(osee_msmc_data_size_to_align);
        osee_msmc_data_start = .;
    } > OCMC_RAM

    .kernel_bss_global (NOLOAD) : ALIGN(8) {
        *(osee_gbl_kernel_bss)
    } > OCMC_RAM

    .kernel_data_global : ALIGN(8) {
        *(osee_gbl_kernel_data)
    } > OCMC_RAM

    msmc_data_stop_align (NOLOAD) : {
        osee_msmc_data_stop = .;
        osee_msmc_data_log2ceil_size = ((osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 5) ? 5 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 6) ? 6 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 7) ? 7 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 8) ? 8 :(osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 9) ? 9 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 10) ? 10 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 11) ? 11 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 12) ? 12 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 13) ? 13 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 14) ? 14 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 15) ? 15 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 16) ? 16 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 17) ? 17 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 18) ? 18 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 19) ? 19 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 20) ? 20 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 21) ? 21 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 22) ? 22 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 23) ? 23 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 24) ? 24 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 25) ? 25 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 26) ? 26 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 27) ? 27 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 28) ? 28 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 29) ? 29 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 30) ? 30 : (osee_msmc_data_stop - osee_msmc_data_start) <= (1 << 31) ? 31 : -1);
        osee_msmc_data_size_to_align = 1 << osee_msmc_data_log2ceil_size;
        . = ALIGN(osee_msmc_data_size_to_align);
        osee_msmc_data_end = .;
    } > OCMC_RAM  

    .startupData : ALIGN(8) {
        *(.startupData)
    } > OCMC_RAM  

    .startupCode : ALIGN(8) {
        *(.startupCode)
    } > OCMC_RAM 

    .bootCode : ALIGN(8) {
        *(.bootCode)
    } > OCMC_RAM  

    .text : ALIGN(8) {
        *(.text)
        *(.text.*)
    } > OCMC_RAM    

    .bss : ALIGN(4) {
        *(.bss)
    } > OCMC_RAM

    .data : ALIGN(128) {
        *(.data)
        *(.data.*)
    } > OCMC_RAM    

    .bss.devgroup.* : ALIGN(4) {
        *(.bss.devgroup.*)
    } > OCMC_RAM

    .const.devgroup.* : ALIGN(4) {
        *(.const.devgroup.*)
    } > OCMC_RAM

    .boardcfg_data : ALIGN(4) 
    {
        *(.boardcfg_data)
    } > OCMC_RAM

    .SciClientBoardCfgSection : ALIGN(128)
    {
        .=ALIGN(128);
        __linker_boardcfg_data_start = .;
        . += 0x100;
        *(.boardcfg_data)
        .=ALIGN(128);
        . += 0x100;
        __linker_boardcfg_data_end = .;
    } > OCMC_RAM

    .stack : ALIGN(4) {
        *(.stack)
    } > OCMC_RAM

    .kernel_bss_percpu (NOLOAD) : ALIGN(8) {
        *(osee_kernel_bss_percpu)
    } > BTCM

    .kernel_data_percpu : ALIGN(8) {
        *(osee_kernel_data_percpu)
    } > BTCM AT > OCMC_RAM

    kernel_code_start_align (NOLOAD) : {
        . = ALIGN(osee_kernel_code_size_to_align);
        osee_kernel_code_start = .;
    } > OCMC_RAM

    .kernel_text : {
        *(.boot)
        *(.kernel_text)
        *(osee_kernel_text)
        *(.gnu.linkonce.t.*)
        *(.plt)
        *(.gnu_warning)
        *(.gcc_execpt_table)
        *(.glue_7)
        *(.glue_7t)
        *(.vfp11_veneer)
        *(.ARM.extab)
        *(.gnu.linkonce.armextab.*)
    } > OCMC_RAM

    OsApplication_DefaultEcucPartition_code_start_align : {
        osee_OsApplication_DefaultEcucPartition_code_start = .;
    } > DDR0_MCU_R5F

    .OsApplication_DefaultEcucPartition_text : ALIGN(8) {
        *(osee_OsApplication_DefaultEcucPartition_text)
        *(*_OsApplication_DefaultEcucPartition_text)
    } > DDR0_MCU_R5F

    OsApplication_DefaultEcucPartition_code_stop_align : {
        osee_OsApplication_DefaultEcucPartition_code_end = .;
    } > DDR0_MCU_R5F

    .text_cpu0 : {
        *(osee_core0_text)
        *(*_core0_text.*)
    } > OCMC_RAM

    .init : {
        KEEP (*(.init))
    } > OCMC_RAM

    .fini : {
        KEEP (*(.fini))
    } > OCMC_RAM

    .interp : {
        KEEP (*(.interp))
    } > OCMC_RAM

    .note-ABI-tag : {
        KEEP (*(.note-ABI-tag))
    } > OCMC_RAM

    .ctors : {
        __CTOR_LIST__ = .;
        ___CTORS_LIST___ = .;
        KEEP (*crtbegin.o(.ctors))
        KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
        KEEP (*(SORT(.ctors.*)))
        KEEP (*(.ctors))
        __CTOR_END__ = .;
        ___CTORS_END___ = .;
    } > OCMC_RAM

    .dtors : {
        __DTOR_LIST__ = .;
        ___DTORS_LIST___ = .;
        KEEP (*crtbegin.o(.dtors))
        KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
        KEEP (*(SORT(.dtors.*)))
        KEEP (*(.dtors))
        __DTOR_END__ = .;
        ___DTORS_END___ = .;
    } > OCMC_RAM

    .fixup : {
        *(.fixup)
    } > OCMC_RAM

    .eh_frame : {
        *(.eh_frame)
    } > OCMC_RAM

    .eh_framehdr : {
        *(.eh_framehdr)
    } > OCMC_RAM

    .gcc_except_table : {
        *(.gcc_except_table)
    } > OCMC_RAM

    kernel_code_stop_align (NOLOAD) : {
        osee_kernel_code_stop = .;
        osee_kernel_code_log2ceil_size = ((osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 5) ? 5 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 6) ? 6 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 7) ? 7 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 8) ? 8 :(osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 9) ? 9 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 10) ? 10 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 11) ? 11 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 12) ? 12 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 13) ? 13 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 14) ? 14 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 15) ? 15 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 16) ? 16 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 17) ? 17 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 18) ? 18 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 19) ? 19 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 20) ? 20 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 21) ? 21 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 22) ? 22 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 23) ? 23 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 24) ? 24 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 25) ? 25 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 26) ? 26 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 27) ? 27 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 28) ? 28 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 29) ? 29 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 30) ? 30 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 31) ? 31 : -1);
        osee_kernel_code_size_to_align = 1 << osee_kernel_code_log2ceil_size;
        . = ALIGN(osee_kernel_code_size_to_align);
        osee_kernel_code_end = .;
    } > OCMC_RAM

    api_code_start_align (NOLOAD) : {
        . = ALIGN(osee_api_code_size_to_align);
        osee_api_code_start = .;
    } > OCMC_RAM
    .api_text : {
        *(osee_api_text)
        *(*_api_text)
        *(*TEXT_SECTION)
    } > OCMC_RAM
    /* .cbuf : {
        *(.cbuf)
    } > MSMC_DATA */
    api_code_stop_align (NOLOAD) : {
        osee_api_code_stop = .;
        osee_api_code_log2ceil_size = ((osee_api_code_stop - osee_api_code_start) <= (1 << 5) ? 5 : (osee_api_code_stop - osee_api_code_start) <= (1 << 6) ? 6 : (osee_api_code_stop - osee_api_code_start) <= (1 << 7) ? 7 : (osee_api_code_stop - osee_api_code_start) <= (1 << 8) ? 8 :(osee_api_code_stop - osee_api_code_start) <= (1 << 9) ? 9 : (osee_api_code_stop - osee_api_code_start) <= (1 << 10) ? 10 : (osee_api_code_stop - osee_api_code_start) <= (1 << 11) ? 11 : (osee_api_code_stop - osee_api_code_start) <= (1 << 12) ? 12 : (osee_api_code_stop - osee_api_code_start) <= (1 << 13) ? 13 : (osee_api_code_stop - osee_api_code_start) <= (1 << 14) ? 14 : (osee_api_code_stop - osee_api_code_start) <= (1 << 15) ? 15 : (osee_api_code_stop - osee_api_code_start) <= (1 << 16) ? 16 : (osee_api_code_stop - osee_api_code_start) <= (1 << 17) ? 17 : (osee_api_code_stop - osee_api_code_start) <= (1 << 18) ? 18 : (osee_api_code_stop - osee_api_code_start) <= (1 << 19) ? 19 : (osee_api_code_stop - osee_api_code_start) <= (1 << 20) ? 20 : (osee_api_code_stop - osee_api_code_start) <= (1 << 21) ? 21 : (osee_api_code_stop - osee_api_code_start) <= (1 << 22) ? 22 : (osee_api_code_stop - osee_api_code_start) <= (1 << 23) ? 23 : (osee_api_code_stop - osee_api_code_start) <= (1 << 24) ? 24 : (osee_api_code_stop - osee_api_code_start) <= (1 << 25) ? 25 : (osee_api_code_stop - osee_api_code_start) <= (1 << 26) ? 26 : (osee_api_code_stop - osee_api_code_start) <= (1 << 27) ? 27 : (osee_api_code_stop - osee_api_code_start) <= (1 << 28) ? 28 : (osee_api_code_stop - osee_api_code_start) <= (1 << 29) ? 29 : (osee_api_code_stop - osee_api_code_start) <= (1 << 30) ? 30 : (osee_api_code_stop - osee_api_code_start) <= (1 << 31) ? 31 : -1);
        osee_api_code_size_to_align = 1 << osee_api_code_log2ceil_size;
        . = ALIGN(osee_api_code_size_to_align);
        osee_api_code_end = .;
    } > OCMC_RAM
    all_const_start_align (NOLOAD) : {
        . = ALIGN(osee_all_const_size_to_align);
        osee_all_const_start = .;
    } > OCMC_RAM
    .rodata : ALIGN(8) {
        *(*_const)
        *(*api_const_64)
        *(*api_const_32)
        *(*api_const_ptr)
        *(*api_const_16)
        *(*api_const_8)
        *(*api_const_bool)
        *(*api_const_unspecified)
        *(*api_const)
        *(*_const_64)
        *(*_const_32)
        *(*_const_ptr)
        *(*_const_16)
        *(*_const_8)
        *(*_const_bool)
        *(*_const_unspecified)
        *(*_postbuildstruct)
        *(*_postbuildconfig)
        *(.rodata)
        *(.rodata.*)
        *(.rodata1)
        *(.rodata1.*)
        *(*CONFIG_SECTION*)
        *(.gnu.linkonce.r.*)
        . = ALIGN(8) ;
        PROVIDE(__clear_table = .);
        LONG(0 + ADDR(.kernel_bss_global)); LONG(SIZEOF(.kernel_bss_global));
        LONG(0 + ADDR(.kernel_bss)); LONG(SIZEOF(.kernel_bss));
        LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss));
        LONG(0 + ADDR(.sbss2)); LONG(SIZEOF(.sbss2));
        LONG(0 + ADDR(.tbss)); LONG(SIZEOF(.tbss));
        LONG(0 + ADDR(.api_bss)); LONG(SIZEOF(.api_bss));
        LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss));
        LONG(0 + ADDR(.OsApplication_DefaultEcucPartition_bss)); LONG(SIZEOF(.OsApplication_DefaultEcucPartition_bss));
        LONG(0 + ADDR(.kernel_bss_cpu0)); LONG(SIZEOF(.kernel_bss_cpu0));
        LONG(0 + ADDR(.api_bss_cpu0)); LONG(SIZEOF(.api_bss_cpu0));
        LONG(-1); LONG(-1);
        PROVIDE(__copy_table = .) ;
        LONG(LOADADDR(.kernel_data_percpu)); LONG(ADDR(.kernel_data_percpu)); LONG(SIZEOF(.kernel_data_percpu));
        LONG(-1); LONG(-1); LONG(-1);
        . = ALIGN(8);
    } > OCMC_RAM
    .stack_sizes : ALIGN(4) {
        osEE_unwind_start = .;
        KEEP (*(.stack_sizes))
        osEE_unwind_end = .;
    } > OCMC_RAM
    all_const_stop_align (NOLOAD) : {
        osee_all_const_stop = .;
        osee_all_const_log2ceil_size = ((osee_all_const_stop - osee_all_const_start) <= (1 << 5) ? 5 : (osee_all_const_stop - osee_all_const_start) <= (1 << 6) ? 6 : (osee_all_const_stop - osee_all_const_start) <= (1 << 7) ? 7 : (osee_all_const_stop - osee_all_const_start) <= (1 << 8) ? 8 :(osee_all_const_stop - osee_all_const_start) <= (1 << 9) ? 9 : (osee_all_const_stop - osee_all_const_start) <= (1 << 10) ? 10 : (osee_all_const_stop - osee_all_const_start) <= (1 << 11) ? 11 : (osee_all_const_stop - osee_all_const_start) <= (1 << 12) ? 12 : (osee_all_const_stop - osee_all_const_start) <= (1 << 13) ? 13 : (osee_all_const_stop - osee_all_const_start) <= (1 << 14) ? 14 : (osee_all_const_stop - osee_all_const_start) <= (1 << 15) ? 15 : (osee_all_const_stop - osee_all_const_start) <= (1 << 16) ? 16 : (osee_all_const_stop - osee_all_const_start) <= (1 << 17) ? 17 : (osee_all_const_stop - osee_all_const_start) <= (1 << 18) ? 18 : (osee_all_const_stop - osee_all_const_start) <= (1 << 19) ? 19 : (osee_all_const_stop - osee_all_const_start) <= (1 << 20) ? 20 : (osee_all_const_stop - osee_all_const_start) <= (1 << 21) ? 21 : (osee_all_const_stop - osee_all_const_start) <= (1 << 22) ? 22 : (osee_all_const_stop - osee_all_const_start) <= (1 << 23) ? 23 : (osee_all_const_stop - osee_all_const_start) <= (1 << 24) ? 24 : (osee_all_const_stop - osee_all_const_start) <= (1 << 25) ? 25 : (osee_all_const_stop - osee_all_const_start) <= (1 << 26) ? 26 : (osee_all_const_stop - osee_all_const_start) <= (1 << 27) ? 27 : (osee_all_const_stop - osee_all_const_start) <= (1 << 28) ? 28 : (osee_all_const_stop - osee_all_const_start) <= (1 << 29) ? 29 : (osee_all_const_stop - osee_all_const_start) <= (1 << 30) ? 30 : (osee_all_const_stop - osee_all_const_start) <= (1 << 31) ? 31 : -1);
        osee_all_const_size_to_align = 1 << osee_all_const_log2ceil_size;
        . = ALIGN(osee_all_const_size_to_align);
        osee_all_const_end = .;
    } > OCMC_RAM
    core0_kernel_ram_start_align (NOLOAD) : {
        . = ALIGN(osee_core0_kernel_ram_size_to_align);
        osee_core0_kernel_ram_start = .;
    } > OCMC_RAM
    OsApplication_DefaultEcucPartition_ram_start_align : {
        osee_OsApplication_DefaultEcucPartition_ram_start = .;
    } > OCMC_RAM
    .OsApplication_DefaultEcucPartition_bss (NOLOAD) : ALIGN(8) {
        *(osee_OsApplication_DefaultEcucPartition_bss)
        *(*_OsApplication_DefaultEcucPartition_bss)
        *(*_OsApplication_DefaultEcucPartition_bss_64)
        *(*_OsApplication_DefaultEcucPartition_bss_32)
        *(*_OsApplication_DefaultEcucPartition_bss_ptr)
        *(*_OsApplication_DefaultEcucPartition_bss_16)
        *(*_OsApplication_DefaultEcucPartition_bss_8)
        *(*_OsApplication_DefaultEcucPartition_bss_bool)
        *(*_OsApplication_DefaultEcucPartition_bss_unspecified)
        *(*_OsApplication_DefaultEcucPartition_postbuildbufbss)
        . = ALIGN(8);
    } > OCMC_RAM
    .OsApplication_DefaultEcucPartition_data : ALIGN(4) {
        osee_OsApplication_DefaultEcucPartition_data_start = .;
        *(osee_OsApplication_DefaultEcucPartition_data)
        *(*_OsApplication_DefaultEcucPartition_data)
        *(*_OsApplication_DefaultEcucPartition_data_64)
        *(*_OsApplication_DefaultEcucPartition_data_32)
        *(*_OsApplication_DefaultEcucPartition_data_ptr)
        *(*_OsApplication_DefaultEcucPartition_data_16)
        *(*_OsApplication_DefaultEcucPartition_data_8)
        *(*_OsApplication_DefaultEcucPartition_data_bool)
        *(*_OsApplication_DefaultEcucPartition_data_unspecified)
        *(*_OsApplication_DefaultEcucPartition_postbuildbuf)
        *(*_OsApplication_DefaultEcucPartition_postbuildbufdata)
    } > OCMC_RAM
    . = ALIGN(64);
    OsApplication_DefaultEcucPartition_ram_stop_align : {
        osee_OsApplication_DefaultEcucPartition_ram_end = .;
    } > OCMC_RAM
    .kernel_bss_cpu0 (NOLOAD) : ALIGN(8) {
        *(osee_core0_bss)
        *(*_core0_bss)
        . = ALIGN(8);
    } > OCMC_RAM
    .kernel_data_cpu0 : ALIGN(4) {
        *(osee_core0_data)
        *(*_core0_data)
    } > OCMC_RAM
    core0_kernel_ram_stop_align (NOLOAD) : {
        osee_core0_kernel_ram_stop = .;
        osee_core0_kernel_ram_log2ceil_size = ((osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 5) ? 5 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 6) ? 6 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 7) ? 7 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 8) ? 8 :(osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 9) ? 9 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 10) ? 10 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 11) ? 11 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 12) ? 12 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 13) ? 13 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 14) ? 14 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 15) ? 15 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 16) ? 16 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 17) ? 17 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 18) ? 18 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 19) ? 19 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 20) ? 20 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 21) ? 21 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 22) ? 22 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 23) ? 23 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 24) ? 24 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 25) ? 25 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 26) ? 26 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 27) ? 27 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 28) ? 28 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 29) ? 29 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 30) ? 30 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 31) ? 31 : -1);
        osee_core0_kernel_ram_size_to_align = 1 << osee_core0_kernel_ram_log2ceil_size;
        . = ALIGN(osee_core0_kernel_ram_size_to_align);
        osee_core0_kernel_ram_end = .;
    } > OCMC_RAM
    kernel_ram_start_align (NOLOAD) : {
        . = ALIGN(osee_kernel_ram_size_to_align);
        osee_kernel_ram_start = .;
    } > OCMC_RAM
    .kernel_bss (NOLOAD) : ALIGN(8) {
        osEE_bss_start = .;
        *(.bss_cpu)
        *(ioc_kernel_bss)
        *(osee_kernel_bss)
        *(osee_core*_kernel_bss)
        *(*_kernel_bss)
        *(.gnu.linkonce.b.*)
        *(COMMON)
        . = ALIGN(8);
        osEE_bss_end = .;
    } > OCMC_RAM
    .tbss (NOLOAD) : ALIGN(8) {
        *(.tbss)
        *(.tbss.*)
        *(.gnu.linkonce.tb.*)
        . = ALIGN(8);
    } > OCMC_RAM
    .sbss (NOLOAD) : ALIGN(8) {
        osEE_sbss_start = .;
        *(.sbss)
        *(.sbss.*)
        *(.gnu.linkonce.sb.*)
        . = ALIGN(8);
        osEE_sbss_end = .;
    } > OCMC_RAM
    .sbss2 (NOLOAD) : ALIGN(8) {
        *(.sbss2)
        *(.sbss2.*)
        *(.gnu.linkonce.sb2.*)
        . = ALIGN(8);
    } > OCMC_RAM
    .kernel_data : ALIGN(4) {
        osee_kernel_data_start = .;
        *(.data_cpu*)
        *(ioc_kernel_data)
        *(osee_kernel_data)
        *(osee_core*_kernel_data)
        *(*_kernel_data)
        *(.gnu.linkonce.d.*)
    } > OCMC_RAM
    .data1 : ALIGN(4) {
        *(.data1)
        *(.data1.*)
    } > OCMC_RAM
    .sdata : ALIGN(4) {
        *(.sdata)
        *(.sdata.*)
        *(.gnu.linkonce.s.*)
    } > OCMC_RAM
    .sdata2 : ALIGN(4) {
        *(.sdata2)
        *(.sdata2.*)
        *(.gnu.linkonce.s2.*)
    } > OCMC_RAM
    .tdata : ALIGN(4) {
        *(.tdata)
        *(.tdata.*)
        *(.gnu.linkonce.td.*)
    } > OCMC_RAM
    .heap (NOLOAD) : ALIGN(64) {
        end = .;
    } > OCMC_RAM
    kernel_ram_stop_align (NOLOAD) : {
        osee_kernel_ram_stop = .;
        osee_kernel_ram_log2ceil_size = ((osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 5) ? 5 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 6) ? 6 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 7) ? 7 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 8) ? 8 :(osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 9) ? 9 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 10) ? 10 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 11) ? 11 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 12) ? 12 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 13) ? 13 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 14) ? 14 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 15) ? 15 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 16) ? 16 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 17) ? 17 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 18) ? 18 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 19) ? 19 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 20) ? 20 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 21) ? 21 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 22) ? 22 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 23) ? 23 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 24) ? 24 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 25) ? 25 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 26) ? 26 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 27) ? 27 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 28) ? 28 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 29) ? 29 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 30) ? 30 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 31) ? 31 : -1);
        osee_kernel_ram_size_to_align = 1 << osee_kernel_ram_log2ceil_size;
        . = ALIGN(osee_kernel_ram_size_to_align);
        osee_kernel_ram_end = .;
            . = ALIGN(8);      
    } > OCMC_RAM

    api_ram_start_align (NOLOAD) : {
        . = ALIGN(osee_api_ram_size_to_align);
        osee_api_ram_start = .;
    } > DDR0_MCU_R5F
    .api_bss (NOLOAD) : ALIGN(8) {
        *(osee_api_bss)
        *(*_api_bss_64)
        *(*_api_bss_32)
        *(*_api_bss_ptr)
        *(*_api_bss_16)
        *(*_api_bss_8)
        *(*_api_bss_bool)
        *(*_api_bss_unspecified)
        *(*_api_bss)
        *(*_api_postbuildbufbss)
        ALIGN(128)
        *(ETH_DATA_NO_INIT_UNSPECIFIED_SECTION)
        .api_data : ALIGN(4) {
        osee_api_data_start = .;
        *(osee_api_data)
        *(*_api_data_ptr)
        *(*_api_data_64)
        *(*_api_data_32)
        *(*_api_data_16)
        *(*_api_data_8)
        *(*_api_data_bool)
        *(*_api_data_unspecified)
        *(*_api_data)
        *(*_api_postbuildbuf)
        *(*_api_postbuildbufdata)
    } > DDR0_MCU_R5F
    api_ram_stop_align (NOLOAD) : {
        osee_api_ram_stop = .;
        osee_api_ram_log2ceil_size = ((osee_api_ram_stop - osee_api_ram_start) <= (1 << 5) ? 5 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 6) ? 6 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 7) ? 7 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 8) ? 8 :(osee_api_ram_stop - osee_api_ram_start) <= (1 << 9) ? 9 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 10) ? 10 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 11) ? 11 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 12) ? 12 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 13) ? 13 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 14) ? 14 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 15) ? 15 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 16) ? 16 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 17) ? 17 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 18) ? 18 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 19) ? 19 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 20) ? 20 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 21) ? 21 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 22) ? 22 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 23) ? 23 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 24) ? 24 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 25) ? 25 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 26) ? 26 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 27) ? 27 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 28) ? 28 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 29) ? 29 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 30) ? 30 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 31) ? 31 : -1);
        osee_api_ram_size_to_align = 1 << osee_api_ram_log2ceil_size;
        . = ALIGN(osee_api_ram_size_to_align);
        osee_api_ram_end = .;
    } > DDR0_MCU_R5F
    core0_api_ram_start_align (NOLOAD) : {
        . = ALIGN(osee_core0_api_ram_size_to_align);
        osee_core0_api_ram_start = .;
    } > DDR0_MCU_R5F
    .api_bss_cpu0 (NOLOAD) : ALIGN(8) {
        *(osee_core0_api_bss)
        *(*_core0_api_bss)
        . = ALIGN(8);
    } > DDR0_MCU_R5F
    .api_data_cpu0 : ALIGN(4) {
        *(osee_core0_api_data)
        *(*_core0_api_data)
    } > DDR0_MCU_R5F
    core0_api_ram_stop_align (NOLOAD) : {
        osee_core0_api_ram_stop = .;
        osee_core0_api_ram_log2ceil_size = ((osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 5) ? 5 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 6) ? 6 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 7) ? 7 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 8) ? 8 :(osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 9) ? 9 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 10) ? 10 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 11) ? 11 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 12) ? 12 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 13) ? 13 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 14) ? 14 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 15) ? 15 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 16) ? 16 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 17) ? 17 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 18) ? 18 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 19) ? 19 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 20) ? 20 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 21) ? 21 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 22) ? 22 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 23) ? 23 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 24) ? 24 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 25) ? 25 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 26) ? 26 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 27) ? 27 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 28) ? 28 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 29) ? 29 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 30) ? 30 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 31) ? 31 : -1);
        osee_core0_api_ram_size_to_align = 1 << osee_core0_api_ram_log2ceil_size;
        . = ALIGN(osee_core0_api_ram_size_to_align);
        osee_core0_api_ram_end = .;
    } > DDR0_MCU_R5F
    os_stack_start_align (NOLOAD) : {
        . = ALIGN(osee_os_stack_size_to_align);
        osee_os_stack_start = .;
    } > DDR0_MCU_R5F
    . += 32;
    . = ALIGN(32);
    osee_OsApplication_DefaultEcucPartition_stack_start = .;
    .OsApplication_DefaultEcucPartition_stack : ALIGN(32) {
        *(osee_OsApplication_DefaultEcucPartition_stack)
        *(*_OsApplication_DefaultEcucPartition_stack)
    } > DDR0_MCU_R5F
    . = ALIGN(32);
    osee_OsApplication_DefaultEcucPartition_stack_end = .;
    . += 32;
    . = ALIGN(32);
    .cpu0.stack (NOLOAD): ALIGN(32) {
        osee_core0_stack_start = .;
        *(osee_core0_sys_stack)
        . = ALIGN(8);
        PROVIDE(osee_core0_sys_stack_top = .);
        . += Mode_SYS_Stack_Size;
        . = ALIGN(8);
        PROVIDE(osee_core0_sys_stack = .);
        PROVIDE(osee_core0_sys_stack_bottom = .);
        osEE_core0_svc_stack_top = .;
        . += Mode_SVC_Stack_Size;
        osEE_core0_svc_stack_bottom = .;
        . = ALIGN(8);
        PROVIDE(osee_core0_svc_stack = .);
        osEE_core0_irq_stack_top = .;
        . += Mode_IRQ_Stack_Size;
        osEE_core0_irq_stack_bottom = .;
        . = ALIGN(8);
        PROVIDE(osee_core0_irq_stack = .);
        osEE_core0_fiq_stack_top = .;
        . += Mode_FIQ_Stack_Size;
        osEE_core0_fiq_stack_bottom = .;
        . = ALIGN(8);
        PROVIDE(osee_core0_fiq_stack = .);
        osEE_core0_abt_stack_top = .;
        . += Mode_EXE_Stack_Size;
        osEE_core0_abt_stack_bottom = .;
        . = ALIGN(8);
        PROVIDE(osee_core0_abt_stack = .);
        osEE_core0_und_stack_top = .;
        . += Mode_EXE_Stack_Size;
        osEE_core0_und_stack_bottom = .;
        . = ALIGN(8);
        PROVIDE(osee_core0_und_stack = .);
        osee_core0_stack_end = .;
    } > DDR0_MCU_R5F
    os_stack_stop_align (NOLOAD) : {
        osee_os_stack_stop = .;
        osee_os_stack_log2ceil_size = ((osee_os_stack_stop - osee_os_stack_start) <= (1 << 5) ? 5 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 6) ? 6 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 7) ? 7 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 8) ? 8 :(osee_os_stack_stop - osee_os_stack_start) <= (1 << 9) ? 9 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 10) ? 10 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 11) ? 11 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 12) ? 12 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 13) ? 13 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 14) ? 14 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 15) ? 15 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 16) ? 16 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 17) ? 17 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 18) ? 18 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 19) ? 19 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 20) ? 20 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 21) ? 21 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 22) ? 22 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 23) ? 23 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 24) ? 24 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 25) ? 25 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 26) ? 26 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 27) ? 27 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 28) ? 28 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 29) ? 29 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 30) ? 30 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 31) ? 31 : -1);
        osee_os_stack_size_to_align = 1 << osee_os_stack_log2ceil_size;
        . = ALIGN(osee_os_stack_size_to_align);
        osee_os_stack_end = .;
    } > DDR0_MCU_R5F
    /* .jcr : {
        *(.jcr)
    } > DDR0_MCU_R5F
    .got : {
        *(.got)
        *(.got.plt)
    } > DDR0_MCU_R5F
    .preinit_array : {
        KEEP (*(SORT(.preinit_array.*)))
        KEEP (*(.preinit_array))
    } > DDR0_MCU_R5F
    .init_array : {
        KEEP (*(SORT(.init_array.*)))
        KEEP (*(.init_array))
    } > DDR0_MCU_R5F
    .fini_array : {
        KEEP (*(SORT(.fini_array.*)))
        KEEP (*(.fini_array))
    } > DDR0_MCU_R5F
    .ARM.attributes : {
        *(.ARM.attributes)
    } > DDR0_MCU_R5F */

    /DISCARD/ : {
        *(.ARM.exidx*)
        *(.gnu.linkonce.armexidix.*.*)
    }    
}

/*# ###*B*###
 * Erika Enterprise, version 3
 * 
 * Copyright (C) 2017-2019 Evidence s.r.l.
 * Copyright (C) 2019-  Huawei Technologies Co., Ltd. and its Affiliates
  # ###*E*###
*/

/**
 * \file  ee_cortex_r_boot.S
 * \brief Start-up code
 *
 *
 * \author VOS
 * \date    2019
 */

#include "ee_cfg.h"
#include "ee_cortex_r_tcm.h"
#include "ee_cortex_r_asm.h"

#if (defined(OSEE_C_LIB))
    .global __libc_init_array
    .global __libc_fini_array
    .global exit
#endif /* OSEE_C_LIB */

/* Entry point for application  */
    .global main

/*=============================================================================
                                   Utility Macros
  ===========================================================================*/
/* SCTLR Macros: */
  .equ  SCTLR_M_BIT,          0x00000001 /* MMU/MPU enable bit        */
  .equ  SCTLR_A_BIT,          0x00000002 /* Alignement Checking Bit   */
  .equ  SCTLR_C_BIT,          0x00000004 /* Data & Unified Cache Bit  */
  .equ  SCTLR_I_BIT,          0x00001000 /* Instruction Cache Bit     */
  .equ  SCTLR_BR_BIT,         (1 << 17)  /* MPU Background Region     */

/*=============================================================================
                       Entry point for the Reset handler
 ============================================================================*/
     SECTION(.startup)
    .align 8
  
    .global osEE_cortex_r_C_init
    .global _reset
    ASM_FUNC_START(_reset)
_reset:
/*=============================================================================
                       reset sctrl and cpsr register
  ===========================================================================*/
/* Change CPSR.MODE to HYP */
    ldr   r0, .cpsr_int_value
    msr   CPSR_cxsf, r0

/* Read SCTLR CP15 Control Register */
    mrc   p15, 0, r0, c1, c0, 0
/* Disable MPU (M bit) & data cache (C bit) */
    bic   r0, r0, #SCTLR_M_BIT | SCTLR_C_BIT
/* Disable instruction cache (I bit) [2 instructions needed, mask too big] */
    bic   r0, r0, #SCTLR_I_BIT
/* Ensure all previous loads/stores have completed */
    dsb
/* Write Back SCTLR CP15 Control Register */
    mcr   p15, 0, r0, c1, c0, 0
/* Ensure subsequent instructionss execute wrt new MPU settings */
    isb

/*=============================================================================
               Cortex-R5 implementation-specific configuration
  ===========================================================================*/
/* SIZE field mask */
    mov   r1, #0x3C
/* Read from FLASHIFREGIONR */
    mrc   p15, #0, r0, c15, c0, #1
/* Extract SIZE and set flags */
    ands  r2, r0, r1
    beq L1
/* Set enable bit if SIZE=!0x0 */
    orr r0, r0, #0x1
/* Write r0 to FLASHIFREGIONR if SIZE=!0x0 */
    mcr p15, #0, r0, c15, c0, #1
L1:
/* Read from PERIPHPREGIONR */
    mrc   p15, #0, r0, c15, c0, #0
/* Extract SIZE and set flags */
    ands  r2, r0, r1
    beq L2
/* Set enable bit if SIZE=!0x0 */
    orr r0, r0, #0x1
/* Write r0 to PERIPHPREGIONR if SIZE=!0x0 */
    mcr p15, #0, r0, c15, c0, #0
L2:
/* Init Stack Pointers */
.start_sp_set:
    cps   #CPSR_MODE_SYS
    mrc   p15, 0, r0, c0, c0, 5
    mov   r1, #0xFFFF
    ands  r0, r0, r1

#if (defined(OSEE_CORE0_VALID))
    mov   r1, #OSEE_CORE0_PHY_ID
    cmp   r0, r1
    beq   core0_sp_set
    b     .finish_core0_sp_set
core0_sp_set:
    ldr   sp, =osee_core0_sys_stack

    cps   #CPSR_MODE_UND
    ldr   sp, =osee_core0_und_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_ABT
    ldr   sp, =osee_core0_abt_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_FIQ
    ldr   sp, =osee_core0_fiq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_IRQ
    ldr   sp, =osee_core0_irq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_SVC
    ldr   sp, =osee_core0_svc_stack
    cps   #CPSR_MODE_SYS
    b     .finish_sp_set

.finish_core0_sp_set:
#endif

#if (defined(OSEE_CORE1_VALID))
    mov   r1, #OSEE_CORE1_PHY_ID
    cmp   r0, r1
    beq   core1_sp_set
    b     .finish_core1_sp_set
core1_sp_set:
    ldr   sp, =osee_core1_sys_stack

    cps   #CPSR_MODE_UND
    ldr   sp, =osee_core1_und_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_ABT
    ldr   sp, =osee_core1_abt_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_FIQ
    ldr   sp, =osee_core1_fiq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_IRQ
    ldr   sp, =osee_core1_irq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_SVC
    ldr   sp, =osee_core1_svc_stack
    cps   #CPSR_MODE_SYS
    b     .finish_sp_set

.finish_core1_sp_set:
#endif

#if (defined(OSEE_CORE2_VALID))
    mov   r1, #OSEE_CORE2_PHY_ID
    cmp   r0, r1
    beq   core2_sp_set
    b     .finish_core2_sp_set
core2_sp_set:
    ldr   sp, =osee_core2_sys_stack

    cps   #CPSR_MODE_UND
    ldr   sp, =osee_core2_und_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_ABT
    ldr   sp, =osee_core2_abt_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_FIQ
    ldr   sp, =osee_core2_fiq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_IRQ
    ldr   sp, =osee_core2_irq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_SVC
    ldr   sp, =osee_core2_svc_stack
    cps   #CPSR_MODE_SYS
    b     .finish_sp_set

.finish_core2_sp_set:
#endif

#if (defined(OSEE_CORE3_VALID))
    mov   r1, #OSEE_CORE3_PHY_ID
    cmp   r0, r1
    beq   core3_sp_set
    b     .finish_core3_sp_set
core3_sp_set:
    ldr   sp, =osee_core3_sys_stack

    cps   #CPSR_MODE_UND
    ldr   sp, =osee_core3_und_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_ABT
    ldr   sp, =osee_core3_abt_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_FIQ
    ldr   sp, =osee_core3_fiq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_IRQ
    ldr   sp, =osee_core3_irq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_SVC
    ldr   sp, =osee_core3_svc_stack
    cps   #CPSR_MODE_SYS
    b     .finish_sp_set

.finish_core3_sp_set:
#endif

#if (defined(OSEE_CORE4_VALID))
    mov   r1, #OSEE_CORE4_PHY_ID
    cmp   r0, r1
    beq   core4_sp_set
    b     .finish_core4_sp_set
core4_sp_set:
    ldr   sp, =osee_core4_sys_stack

    cps   #CPSR_MODE_UND
    ldr   sp, =osee_core4_und_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_ABT
    ldr   sp, =osee_core4_abt_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_FIQ
    ldr   sp, =osee_core4_fiq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_IRQ
    ldr   sp, =osee_core4_irq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_SVC
    ldr   sp, =osee_core4_svc_stack
    cps   #CPSR_MODE_SYS
    b     .finish_sp_set

.finish_core4_sp_set:
#endif

#if (defined(OSEE_CORE5_VALID))
    mov   r1, #OSEE_CORE5_PHY_ID
    cmp   r0, r1
    beq   core5_sp_set
    b     .finish_core5_sp_set
core5_sp_set:
    ldr   sp, =osee_core5_sys_stack

    cps   #CPSR_MODE_UND
    ldr   sp, =osee_core5_und_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_ABT
    ldr   sp, =osee_core5_abt_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_FIQ
    ldr   sp, =osee_core5_fiq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_IRQ
    ldr   sp, =osee_core5_irq_stack
    cps   #CPSR_MODE_SYS

    cps   #CPSR_MODE_SVC
    ldr   sp, =osee_core5_svc_stack
    cps   #CPSR_MODE_SYS
    b     .finish_sp_set

.finish_core5_sp_set:
#endif

.finish_sp_set:

/*=============================================================================
                                 Cache invalidation.
    However Cortex-R52 provides CFG signals to invalidate cache automatically
    out of reset (CFGL1CACHEINVDISx)
  ===========================================================================*/
/* N.B. In Cortex-R52 You cannot invalidate all Datat Caches how
        it was possible in Cortex-R{4,5} */
/* Complete all outstanding explicit memory operations */
    dsb
/* Invalidate I-Cache (ICIALLU: Invalidate all Instruction Caches to PoU) */
    mov   r0, #0
    mcr   p15, #0, r0, c7, c5, #0

/* Invalidate Data/Unified Caches */
/* Read CLIDRCache Level ID Register */
    mrc   p15, #1, r0, c0, c0, #1
/* Extract coherency level */
    ands  r3, r0, #0x07000000
/* Total cache levels >> on the LSB (barrel shifter) */
    mov   r3, r3, LSR #23
/* If 0, no need to clean */
    beq   .LCache_Data_Finished

/* R10 holds current cache level */
    mov   r10, #0
.LCache_Level_Loop:
/* R2 holds cache "Set" position (barrel shifter) */
    add   r2, r10, r10, LSR #1
/* Bottom 3 bits are the Cache-type for this level (barrel shifter) */
    mov   r1, r0, LSR r2
/* Isolate those lower 3 bits */
    and   r1, r1, #7
    cmp   r1, #2
/* No cache or only instruction cache at this level */
    blt   .LCache_Level_Skip

/* Write the Cache Size selection register (CSSELR) +
   ISB to sync the change to the CacheSizeID reg */
    mcr   p15, #2, r10, c0, c0, #0
    isb
/* Reads current Cache Size ID register (CCSIDR) */
    mrc   p15, #1, r1, c0, c0, #0
/* Extract the line size field */
    and   r2, r1, #7
/* Add 4 for the line size offset (log2 16 bytes) */
    add   r2, r2, #4

/* R4 is the Associativity: max number on the way size (right aligned/LSB) */
    ldr   r4, .cache_mask_value1
    ands  r4, r4, r1, LSR #3

/* R5 is the bit position of the way size increment */
    clz   r5, r4

/* R7 is the max number of the index size (right aligned) */
    ldr   r7, .cache_mask_value2
    ands  r7, r7, r1, LSR #13

.LCache_Ways_Loop:
/* R9 working copy of the max way size (right aligned) */
    mov   r9, r4

#if (defined(__THUMB__))
.LCache_Set_Loop:
 /* Factor in the Way number and cache number into R11 */
    lsl   r12, r9, r5
    orr   r11, r10, r12
/* Factor in the Set number */
    lsl   r12, r7, r2
    orr   r11, r11, r12
#else
.LCache_Set_Loop:
/* Factor in the Way number and cache number into R11 */
    orr   r11, r10, r9, LSL r5
/* Factor in the Set number */
    orr   r11, r11, r7, LSL r2
#endif

/* Invalidate by Set/Way (DCISW) */
    mcr   p15, #0, r11, c7, c6, #2

/* Decrement the Way number */
    subs  r9, r9, #1
    bge   .LCache_Set_Loop

/*  Decrement the Set number */
    subs  r7, r7, #1
    bge   .LCache_Ways_Loop

.LCache_Level_Skip:
/* Increment the cache level number, bits [3:1] so increment is 2 */
    add   r10, r10, #2
    cmp   r3, r10
    bgt   .LCache_Level_Loop

.LCache_Data_Finished:

#if (defined(OSEE_FPU_ENABLE))
/*=============================================================================
                                    Enable VFP
  ===========================================================================*/
/*
 * Enable access to VFP by enabling access to Coprocessors 10 and 11.
 * Enables Full Access i.e. in both privileged and non privileged modes
 */
/* Read Coprocessor Access Control Register (CPACR) */
    mrc   p15, #0, r0, c1, c0, #2
/* Enable access to CP 10 & 11 */
    orr   r0, r0, #(0xf << 20)
/* Write Back Coprocessor Access Control Register (CPACR) */
    mcr   p15, #0, r0, c1, c0, #2
/* Synchronize processor status */
    isb
/* Enable FPU Access. FPEXC register, EN bit set */
    vmrs  r3, fpexc
    orr   r1, r3, #(1<<30)
    vmsr  fpexc, r1
#endif /* OSEE_FPU_ENABLE */

/*=============================================================================
                         Reset and start Cycle Counter
  ===========================================================================*/
    mov   r0, #0x80000000         /* Clear overflow & Enable cycle counter MASK */
    mov   r1, #0xd                /* D, C, E */
/* Clear Overflow */
    mcr   p15, #0, r0, c9, c12, #3
    mcr   p15, #0, r1, c9, c12, #0
/* Enable Cycle Counter */
    mcr   p15, #0, r0, c9, c12, #1

    blx   osEE_cortex_r_fix_boot_mpu_setup

/* Read System Control Register (SCTRL) */
    mrc p15, 0, r0, c1, c0, 0
/* Prepare the MASK with VE, M & BR bits */
    ldr r1, .sctlr_mpu_setup
/* Set the mask on previous SCTRL value*/
    orr r0, r0, r1
/* Ensure all previous loads/stores have completed */
    dsb
/* Write System Control Register */
    mcr p15, 0, r0, c1, c0, 0
/* Ensure subsequent insts execute wrt new MPU settings */
    isb

/* TCM init */
    blx   osEE_cortex_r_tcm_init

/* Run C initialization */
    blx   osEE_cortex_r_C_init

/*=============================================================================
                                  MPU Configuration
=============================================================================*/
    blx   osEE_cortex_r_fix_mpu_setup

    ldr r1, =0x0
    mcr   p15, 0, r1, c6, c2, 0     /* Write RGNR to select region 0 */
    ldr r1, =0x1204                 /* Config background region with strongly-ordered */
    mcr   p15, 0, r1, c6, c1, 4     /* Write RACR0 */

/*=============================================================================
                        Enable Cache
=============================================================================*/
/* Read System Control Register (SCTRL) */
    mrc p15, 0, r0, c1, c0, 0
/* Prepare the MASK with I, C bits */
    ldr r1, .sctlr_cache_setup
/* Set the mask on previous SCTRL value*/
    orr r0, r0, r1
/* Ensure all previous loads/stores have completed */
    dsb
/* Write System Control Register */
    mcr p15, 0, r0, c1, c0, 0
/* Ensure subsequent insts execute wrt new MPU settings */
    isb

/*=============================================================================
                       Enable asynchronous aborts Exception
  ===========================================================================*/
    mrs r0, cpsr
    bic r0, r0, #(1 << 8)
    msr CPSR_cxsf, r0 

/*=============================================================================
                              libc initialization
  ===========================================================================*/
#if (defined(OSEE_C_LIB))
/* Run global constructors */
    blx   __libc_init_array
/* Jump to main C code */
    blx   main
/* Cleanup global constructors */
    blx   __libc_fini_array
/* Libc exit */
    blx   exit
#else
/* Jump to main C code */
    blx   main
#endif /* OSEE_C_LIB */
.Lpanic:
    dsb         /* Clear all pending data accesses */
    wfi         /* Go to sleep */
    b   .Lpanic /* We should never get here */
    ASM_FUNC_END(_reset)

/*=============================================================================
                              init value
  ===========================================================================*/
#if (defined(OSEE_HIGH_VECTORS))
.sctlr_mpu_setup    : .long (SCTRL_VE_BIT | SCTRL_V_BIT | SCTRL_BR_BIT | SCTRL_M_BIT)
#else
.sctlr_mpu_setup    : .long (SCTRL_VE_BIT | SCTRL_BR_BIT | SCTRL_M_BIT)
#endif

.sctlr_cache_setup  : .long (SCTRL_I_BIT | SCTRL_C_BIT)
.cpsr_int_value     : .long 0x000001D3

.cache_mask_value1: .long  0x3FF
.cache_mask_value2: .long  0x7FFF

您好！

链接器和 boot.S 文件中的大部分代码看起来用于 Cortex R 内核 R5F。 但您将引导 Cortex A 内核 A72。 您是否能够确认该代码与 A72兼容？

我们不像对 R5F 那样支持 A72裸机或 RTOS 加载。 我们过去提供这种支持、您可以将其视为 RTOS SDK 的一部分：

/home/a0226667/sdk/ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/csl/arch/a53

在这里、您可以找到过去用于在引导启动期间初始化 A72内核的启动文件。 请查看这是否有用。

但自从编译器从 TI CGT 迁移到 LLVM Clang 编译器后、这种方法不再受支持或使用。

请支持以下问题：

1) 1)您正在使用哪个编译器？

2) 2)您是否参考了任何特定的 SDK 版本？

3) 3)我看到启动代码中显示" Cortex-R5实现特定配置"的注释、该代码是否适用于其他 A72内核？

此致、

Erick