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您好!
您能帮助我从 PRU 内核访问 DDR 吗?
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此常见问题解答中的信息适用于所有具有 PRU_ICSSG 的 Sitara 处理器:AM24x、AM64x、AM65x。 在 AM64x 上测试了该示例。
此常见问题解答的基本概念也适用于采用其他类型 PRU 子系统的 Sitara 处理器:
AM335x、AM437x、AM57x:
有关如何从 CCS 或 Linux 内核初始化 PRU 内核的信息、请参阅 PRU 入门实验。 这些较旧的 PRU-ICSS 器件需要先启用 OCP 端口、然后再允许在 PRU 子系统之外进行读取和写入。 有关启用 OCP 端口的示例、请参考相关器件的 RPMsg_Echo_Interrupt 固件: https://git.ti.com/cgit/pru-software-support-package/pru-software-support-package/tree/examples/am335x/PRU_RPMsg_Echo_Interrupt0/main.c
AM62x: 有关如何从 CCS 或 Linux 内核初始化 PRU 内核的信息、请参阅 PRU 入门实验。
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有关多核主题的更多信息、请参阅 Sitara 多核开发和文档常见问题解答。
有关 PRU 的"入门"信息、包括如何从 CCS 或 Linux 内核初始化 PRU 内核、请参阅 PRU 入门实验。
此示例将使用 IEP 计时器对存储器访问进行时间戳记。 但是、PRU_CYCLE 寄存器也可用于计算存储器访问占用的时钟周期数。 有关使用 PRU_CYCLE 寄存器的详细信息、请参考 这篇文章。
前提条件:
/* * Copyright (C) 2018-2021 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include <stdio.h> #include <kernel/dpl/DebugP.h> #include "ti_drivers_config.h" #include "ti_drivers_open_close.h" #include "ti_board_open_close.h" void hello_world_main(void *args) { /* Open drivers to open the UART driver for console */ Drivers_open(); Board_driversOpen(); DebugP_log("Hello World!\r\n"); while(1); Board_driversClose(); Drivers_close(); }
请参阅 TRM 第6.4.12节 PRU_ICSSG_IEP 了解 IEP 时间戳
; Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/ ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions ; are met: ; ; Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; ; Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the ; distribution. ; ; Neither the name of Texas Instruments Incorporated nor the names of ; its contributors may be used to endorse or promote products derived ; from this software without specific prior written permission. ; ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;************************************************************************************ ; File: main.asm ; ; Brief: Template asm file example ;************************************************************************************ ; CCS/makefile specific settings .retain ; Required for building .out with assembly file .retainrefs ; Required for building .out with assembly file .global main .sect ".text" ;************************************* includes ************************************* ; icss_constant_defines.inc: Defines symbols corresponding to Constant Table Entries .include "icss_constant_defines.inc" .asg R2, IEP_CFG_REG .asg R3, IEP_COUNT_REG0 .asg R4, IEP_COUNT_REG1 .asg R8, TEMP_REG ;******** ;* MAIN * ;******** main: init: ;---------------------------------------------------------------------------- ; Clear the register space ; Before begining with the application, make sure all the registers are set ; to 0. PRU has 32 - 4 byte registers: R0 to R31, with R30 and R31 being special ; registers for output and input respectively. ;---------------------------------------------------------------------------- ; Give the starting address and number of bytes to clear. zero &r0, 120 ;---------------------------------------------------------------------------- ; Constant Table Entries Configuration ; Sample code to configure Constant Table Entries. ;---------------------------------------------------------------------------- ; Configure the Constant Table entry C28 to point to start of shared memory ; PRU_ICSSG Shared RAM (local-C28) : 00nn_nn00h, nnnn = c28_pointer[15:0] ; By default it is set to 0000_0000h so it will point to DMEM0 address ldi TEMP_REG, 0x0100 sbco &TEMP_REG, ICSS_PRU_CTRL_CONST, 0x28, 2 ; Load 32 bit value to TEMP_REG reg ; To load values greater than 16 bits, we use ldi32 which performs ldi 2 times ; - for lsb 16 bits and then for msb 16 bits ldi32 TEMP_REG, 0x12345678 ;---------------------------------------------------------------------------- ; Reading and Writing latency calculation for DDR from PRU ;---------------------------------------------------------------------------- ldi32 R15, 0x80000000 ; DDR base address ;ldi R15.w0, 0 ldi32 R5 ,0x04 ; data to write in DDR ldi32 R6, 0x00 ; data to read from DDR ldi32 R7, 0x00; counter status ldi32 R8, 0x00 ; counter value1 ldi32 R9, 0x00 ; counter value2 ldi32 R10, 0x00 ; counter value3 ;---------------------------------------------------------------------------- ; Initiaizae IEP ;---------------------------------------------------------------------------- ;IEP_CNT_ENABLE lbbo R7, ICSS_IEP1_0_CONST, 0, 4 OR R7, R7, 0x00000001 sbbo R7, ICSS_IEP1_0_CONST, 0, 4 ;Read IEP_COUNT_REG0 lbbo R8, ICSS_IEP1_0_CONST, 0x10, 4 ; T0 in ns ; writing R5 => DDR => R6 sbbo &R5, R15, 0, 0x02 ;Read IEP_COUNT_REG0 lbbo R9, ICSS_IEP1_0_CONST, 0x10, 4 ; T1 in ns ; Reading DDR => R6 lbbo &R6, R15, 0, 0x02 ;Read IEP_COUNT_REG0 lbbo R8, ICSS_IEP1_0_CONST, 0x10, 4 ; T2 in ns ; T1-T0 - 3 PRU_CYCLE = DDR Write Time Latency ; T2-T1 - 3 PRU_CYCLE = DDR Read Time Latency ; Write 4 byte register value to DMEM0 at offset 0x14 sbco &TEMP_REG, ICSS_DMEM0_CONST, 0x14, 4 ; Write 3 byte register value to DMEM1 at offset 0x10 sbco &TEMP_REG, ICSS_DMEM1_CONST, 0x10, 3 ; Write 2 byte register value to SMEM0 at offset 0x22 sbco &TEMP_REG, ICSS_SMEM_CONST, 0x22, 2 halt ; end of program
此致