[参考译文] AM6442：了解捕获的 PPS 时间戳

#include <stdint.h>

#include "./Dependencies/intc_map_0.h"
#include "./Dependencies/resource_table.h"
#include "./pru_registers.h"  // __R30 and __R31, avoid IDE warnings.

#define SHARED_ICSSG_MEM (0x10000)
volatile uint32_t *icssg_shared_mem_ = (uint32_t *)SHARED_ICSSG_MEM;

void HW_WR_REG32(uint32_t addr, uint32_t value) {
  *(volatile uint32_t *)((uintptr_t)addr) = value;
}

inline void pad_config_aka_dtb() {
  HW_WR_REG32(0x00a40034, 0x010016);
  HW_WR_REG32(0x00a40038, 0x010016);
  HW_WR_REG32(0x00a4003C, 0x010016);
  HW_WR_REG32(0x00a40040, 0x010016);
  // pin mux for LATCH_IN - time sync router PRG1_IEP0_EDC_LATCH_IN0
  HW_WR_REG32(0x000F4100, 0x00040002);
  //  time sync router PRG1_IEP0_EDC_LATCH_IN1
  HW_WR_REG32(0x00a40028, 0x00010009);
}

void reset_counter_iep_iep1() {
  /* Disable counter */
  CT_IEP1.global_cfg_reg_bit.cnt_enable = 0;
  /* 64 bits? */
  CT_IEP1.cmp_cfg_reg_bit.shadow_en = 0;
  /* Reset Count register */
  CT_IEP1.count_reg0_bit.count_lo = 0xFFFFFFFF;
  CT_IEP1.count_reg1_bit.count_hi = 0xFFFFFFFF;
  /* Clear overflow status register */
  CT_IEP1.global_status_reg_bit.cnt_ovf = 1;
}

void configure_counter_iep1() {
  CT_IEP1.cmp_cfg_reg_bit.cmp_en = 0;
  CT_IEP1.compen_reg_bit.compen_cnt = 0;
  CT_IEP1.global_cfg_reg_bit.default_inc = 1;
  CT_IEP1.global_cfg_reg_bit.cnt_enable = 1;
}

void main() {
  pad_config_aka_dtb();
  reset_counter_iep_iep1();
  configure_counter_iep1();

  CT_IEP1.cap_cfg_reg = 0x0003FFC0;

  uint32_t reg0 = CT_IEP1.capr6_reg0;
  uint32_t reg1 = CT_IEP1.capr6_reg1;
  uint32_t reg2 = CT_IEP1.cap_status_reg;

  *(icssg_shared_mem_) = 0;
  *(icssg_shared_mem_ + 2) = reg0;
  *(icssg_shared_mem_ + 3) = reg1;

  while (1) {
    reg2 = CT_IEP1.cap_status_reg;
    reg0 = CT_IEP1.capr6_reg0;
    reg1 = CT_IEP1.capr6_reg1;

    if ((*(icssg_shared_mem_ + 2) != reg0 ||
         (*(icssg_shared_mem_ + 3) != reg1))) {
      *(icssg_shared_mem_ + 4) = reg2;

      *(icssg_shared_mem_) += 1;
      *(icssg_shared_mem_ + 2) = reg0;
      *(icssg_shared_mem_ + 3) = reg1;
    }
  }
}

#include <iostream>
#include <fcntl.h>
#include <sys/mman.h>
#include <unistd.h>
#include <cstdint>

int main(){
    const size_t PAGE_SIZE = sysconf(_SC_PAGE_SIZE);
    const off_t BASE_ADDR  = 0x30090000 & ~(PAGE_SIZE - 1);
    int fd = open("/dev/mem", O_RDONLY | O_SYNC);
    void* map = mmap(NULL, PAGE_SIZE, PROT_READ, MAP_SHARED, fd, BASE_ADDR);

    volatile uint32_t* mem = (volatile uint32_t*)map;
    auto off = (0x30090000 - BASE_ADDR) / sizeof(uint32_t);

    uint32_t prevVal = 0xFFFFFFFF; 
    uint64_t prevCount = 0;

    while(true){
        uint32_t val = mem[off];
        if(val != prevVal){
            uint64_t low  = mem[off + 2]; 
            uint64_t high = mem[off + 3];
            uint64_t cnt  = (high << 32) | low;
            std::cout << "mem0x0Count: " << val
                      << ", mem0x8R0: "   << cnt
                      << ", Diff: "       << (cnt - prevCount)
                      << std::endl;
            prevVal   = val;
            prevCount = cnt;
        } else usleep(50000);
    }

    munmap(map, PAGE_SIZE);
    close(fd);
    return 0;
}

mem0x0Count: 0, mem0x8R0: 8399040269, Diff: 8399040269
mem0x0Count: 1, mem0x8R0: 570425132, Diff: 18446744065880936479
mem0x0Count: 2, mem0x8R0: 820425132, Diff: 250000000
mem0x0Count: 3, mem0x8R0: 1070425132, Diff: 250000000
mem0x0Count: 4, mem0x8R0: 1320425132, Diff: 250000000
mem0x0Count: 5, mem0x8R0: 1570425132, Diff: 250000000
mem0x0Count: 6, mem0x8R0: 1820425132, Diff: 250000000
mem0x0Count: 7, mem0x8R0: 2070425132, Diff: 250000000

mem0x0Count: 147, mem0x8R0: 36771615672, Diff: 250001539
mem0x0Count: 148, mem0x8R0: 37021617218, Diff: 250001546
mem0x0Count: 149, mem0x8R0: 37271618771, Diff: 250001553
mem0x0Count: 150, mem0x8R0: 37521620320, Diff: 250001549
mem0x0Count: 151, mem0x8R0: 37771621871, Diff: 250001551
mem0x0Count: 152, mem0x8R0: 38021623426, Diff: 250001555
mem0x0Count: 153, mem0x8R0: 38271624987, Diff: 250001561
mem0x0Count: 154, mem0x8R0: 38521626543, Diff: 250001556
mem0x0Count: 155, mem0x8R0: 38771628098, Diff: 250001555
mem0x0Count: 156, mem0x8R0: 39021629642, Diff: 250001544
mem0x0Count: 157, mem0x8R0: 39271631184, Diff: 250001542

ptp4l[1454.315]: master offset          9 s2 freq   +6358 path delay       409
ptp4l[1455.315]: master offset        -58 s2 freq   +6293 path delay       410
ptp4l[1456.316]: master offset        -59 s2 freq   +6275 path delay       410
ptp4l[1457.316]: master offset          6 s2 freq   +6322 path delay       410
ptp4l[1458.316]: master offset         32 s2 freq   +6350 path delay       407
ptp4l[1459.316]: master offset         37 s2 freq   +6365 path delay       410
ptp4l[1460.316]: master offset         54 s2 freq   +6393 path delay       408
ptp4l[1461.316]: master offset         12 s2 freq   +6367 path delay       408
ptp4l[1462.316]: master offset         17 s2 freq   +6376 path delay       407
ptp4l[1463.316]: master offset        -28 s2 freq   +6336 path delay       407
ptp4l[1464.316]: master offset        -70 s2 freq   +6285 path delay       409
ptp4l[1465.316]: master offset        -67 s2 freq   +6267 path delay       409