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[参考译文] AFE7950EVM:更改 Latte 中的抽取和插值因子后出现错误

Guru**** 2340640 points
请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1499970/afe7950evm-getting-errors-after-changing-decimation-and-interpolation-factor-in-latte

器件型号:AFE7950EVM

工具/软件:

您好:

     我 有一个 Latte 和 TI_204C_IP 的工作配置,具有给定的 Latte 配置和 GTH 配置,那么现在我想把 带宽减半。 因此、我会将抽取率提高到12、然后将内插率提高到48、那么在 Latte 配置和 GTH 配置中、我需要进行哪些更改才能使其正常工作。

在这里 ,我附加的拿铁配置,这是工作的,以前.

'''
Validation :  AFE79xx Library Version 
				v1.67, v1.74
Case			RX					TX						   FB						CLK					Notes
----	-----------------	  -----------------			-----------------			-----------			------------
1		245.76Msps, 24410     491.52Msps, 44210			491.52Msps, 22210			FADC=2949.12M       DAC in interleaved mode
		SerDes=9830.4Mbps     SerDes=9830.4Mbps			SerDes=9830.4Mbps			FDAC=8847.36M
		PLL0, NCO=3500M		  PLL0, NCO=3500M			NCO=3500M                   REF=491.52M
		
2		245.76Msps, 24410     491.52Msps, 44210			491.52Msps, 22210			FADC=2949.12M       DAC in straight mode
		SerDes=9830.4Mbps     SerDes=9830.4Mbps			SerDes=9830.4Mbps			FDAC=8847.36M
		PLL0, NCO=3500M		  PLL0, NCO=3500M			NCO=3500M                   REF=491.52M
'''
setupParams.skipFpga 				= 1
sysParams							=	AFE.systemParams
setupParams.fpgaRefClk 				= 245.76#184.32#
AFE.systemStatus.loadTrims			= 1


sysParams.FRef                    	= 491.52
sysParams.FadcRx                  	= 2949.12
sysParams.FadcFb				  	= 2949.12
sysParams.Fdac                    	= 2949.12*4

sysParams.enableDacInterleavedMode	= False 					#DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd 					= 0		
										# 0- Single TDD Pin for all Channels
										# 1- Separate Control for 2T/2R/1F
										# 2- Separate Control for 1T/1R/1F			

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.RRFMode 					= 0   #4T4R2F FDD mode
sysParams.jesdSystemMode			= [3,3]
										#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb-fb
										#SystemMode 1:	1R1F-FDD						; rx1-rx1-fb-fb
										#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
										#SystemMode 3:	1R								; rx1-rx1-rx1-rx1
										#SystemMode 4:	1F								; fb-fb-fb-fb
										#SystemMode 5:	1R1F-TDD						; rx1/fb-rx1/fb-rx1/fb-rx1/fb
										#SystemMode 8:	1R1F-TDD 1R-FDD	(FB-2Lanes)(RX1 RX2 interchanged)		; rx2/fb-rx2/fb-rx1-rx1


sysParams.jesdLoopbackEn			= 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx                	= ["44210","44210","44210","44210"]	
										# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb                	= ["22210","22210"]
sysParams.LMFSHdTx                	= ["44210","44210","44210","44210"]
sysParams.jesdTxProtocol            = [0,0]
sysParams.jesdRxProtocol            = [0,0]
sysParams.serdesFirmware			= True 		# If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux				= [0,1,2,3,4,5,6,7]	
												# Enter which lanes you want in each location. 
												# Note that across 2T Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesTxLanePolarity		= [True, True, False, False, True, True, False, False]
sysParams.jesdRxLaneMux				= [0,1,2,3,4,5,7,6]	
												# Enter which lanes you want in each location.
												# Note that across 2R Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesRxLanePolarity		= [True, True, True, True, False, False, False, False]
sysParams.jesdRxRbd					= [4, 4]

sysParams.rxJesdTxScr				= [False]*4
sysParams.fbJesdTxScr				= [False]*2
sysParams.jesdRxScr					= [False]*4

sysParams.rxJesdTxK					= [32]*4
sysParams.fbJesdTxK					= [32]*2
sysParams.jesdRxK					= [16]*4 #[32]*4


	
sysParams.txNco0					= 	[[3800,9500],
										[3800,9500],
										[3800,9500],
										[3800,9500]]

sysParams.rxNco0					= 	[[3800,9500],
										[3800,9500],
										[3800,9500],
										[3800,9500]]

sysParams.fbNco0					= 	[2500,2500] #[1800,1800]			#FBA, FBC for NCO0
sysParams.fbNco1					= 	[2500,2500] #[1800,1800]			#FBA, FBC for NCO1
sysParams.fbNco2					= 	[2500,2500] #[1800,1800]			#FBA, FBC for NCO2
sysParams.fbNco3					= 	[2500,2500] #[1800,1800]			#FBA, FBC for NCO3

sysParams.numBandsRx				= [0]*4					# 0 for single, 1 for dual
sysParams.numBandsFb				= [0,0]				
sysParams.numBandsTx				= [0,0,0,0]

sysParams.ddcFactorRx             	= [6]*4			# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb             	= [6]*2
sysParams.ducFactorTx             	= [24]*4

AFE.systemStatus.loadTrims			=1

## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn						=	True#False
lmkParams.inputClk					=	1474.56#737.28
lmkParams.sysrefFreq				=	2949.12/1024
lmkParams.lmkFrefClk				=	True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x0f ## THIS FOR  RTS
#logDumpInst.logFormat				= 0x21 ## THIS  IS FOR BALA SCRIPTS.
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1
device.optimizeWrites				= 0
device.rawWriteLogEn				= 1
lmk.rawWriteLogEn					= 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync			= 0
sysParams.jesdCDLvdsSync			= 0
sysParams.rxJesdTxSyncMux			= [0,0,0,0]
sysParams.fbJesdTxSyncMux			= [0,0]
sysParams.jesdRxSyncMux				= [0,0,0,0]		#[0,0,1,1]
sysParams.syncLoopBack				= True

# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns. 
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent


## The following parameters sets up the GPIOs
sysParams.gpioMapping={
		'H8': 'ADC_SYNC0',
		'H7': 'DAC_SYNC0',
		'N8': 'ADC_SYNC2',
		'N7': 'ADC_SYNC3',
		'H9': 'ADC_SYNC1',
		'G9': 'DAC_SYNC1',
		'N9': 'DAC_SYNC2',
		'P9': 'DAC_SYNC3',
		'P14': 'GLOBAL_PDN',
		'K14': 'FBABTDD',
		'R6': 'FBCDTDD',
		'H15': ['TXATDD','TXBTDD'],
		'V5': ['TXCTDD','TXDTDD'],
		'E7': ['RXATDD','RXBTDD'],
		'R15': ['RXCTDD','RXDTDD']}
		
#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True

sysParams.useSpiSysref = False
#setupParams.skipLmk	=	False
#AFE.LMK.lmkConfig()
sysParams.ncoFreqMode 				=  "FCW"  ##"1KHz" ##"FCW"
AFE.systemStatus.txChainDirectCtrl = 1
## Initiates LMK04828 and AFE79xx Bring-up

setupParams.skipLmk	=	False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()


  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    尊敬的 Dharani:

    更新抽取和内插因子时收到什么错误?  

    要更新这些参数、您应更新以下参数:

    1. sysParams.ddcFactorRx:Rx 抽取因子可以更新为12
    2. sysParams.ddcFactorFb: FB 抽取 因子可以更新为12
    3. sysParams.ducFactorTx:TX 内插因子可以更新为48
    4. setupParams.fpgaRefClk:应根据您的新延迟速率进行更新

    此致、

    David Chaparro  

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    我完全改变了   

    1. sysParams.ddcFactorRx:Rx 抽取因子可以更新为12
    2. sysParams.ddcFactorFb: FB  抽取 因子可以更新为12
    3. sysParams.ducFactorTx:TX 内插因子可以更新为48
    4. 但我将  setupParams.fpgaRefClk 仅保留为245.76、我需要更新什么值?以及如何   根据新通道速率计算 setupParams.fpgaRefClk 的值?

    这里是我得到的错误,而我只更改了抽取,插值率的 RX , TX , FB。

    我尝试给我的  setupParams.fpgaRefClk 使用122.88,然后在 LMK_Config.py 编程后,我正在应用重置序列(序列是正确的),但 QPLL0 没有锁定,我没有在 QPLL0中得到3个值。 除了 setupParams.fpgaRefClk = 245.76 ,对于 setupParams.fpgaRefClk 的任何其他剩余值 我没有得到 qpll0锁定为什么? 我必须要做的是什么。 在这里、我还附加了 GTH 设置以供参考。

       
    这里是我的 GTH 设置,你能告诉我基于什么设置我得到了实际的参考时钟,通道速率值在我的 GTH 收发器.