[参考译文] AFE7950EVM：DAC 输出端为低功耗

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https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1216051/afe7950evm-low-power-at-dac-output

器件型号：AFE7950EVM

大家好、

在 AFE7950EVM 的测试过程中、我最近遇到了输出功率问题。

我在模拟中继器配置中运行 AFE7950EVM、其中、在9.5GHz 的 ADC D 正弦波信号下会产生-10dBm 的功率、而将此输入转发到的 DAC D 输出的 NCO 设置为9.5GHz。频谱分析仪捕获的信号如下图所示。

似乎 DAC 输出(功率为-70dBm)比在输入端发送到 ADC 的值低大约60dB、我不太明白这种损耗来自哪里。

我将9.5GHz 用作 DAC 和 ADC NCO 频率、因为我知道 AFE7950EVM 匹配网络的设计目标是9.5GHz。

请注意、Latte 脚本中没有更改 Tx/Rx DSA 设置的默认值、因为 Latte 脚本严格遵循模拟中继器配置。

请您提供一些有关此行为的见解吗？

此致、

Željko μ A

2 年多前

0 admin 2 年多前

TI__Guru**** 2470720 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好！Željko

输出功率太低。能否仔细检查一下是否已连接到 ADC D 和 DAC D？您是否也可以尝试其他通道？

请分享您使用的脚本。我们将对其进行验证。

此致、

Vijay

0 admin 2 年多前

TI__Guru**** 2470720 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Vijay、您好！

实际上、ADC D (来自-10 dBm 输出功率的外部正弦波发生器)和 DAC D (到频谱分析仪)已正确连接(无松散连接)。如果我尝试其他 DAC、则频谱分析仪上只有本底噪声。

下面是我使用的代码：

script0.py

##########               Board initialization procedure               ##########

mainWindow.clearSession()
base_directory = "C:\\Users\\laboadmin\\Documents\\Texas Instruments\\Afe79xxLatte\\projects\\AFE79xx\\bringup\\"
mainWindow.runFile(base_directory + r"setup.py")
mainWindow.runFile(base_directory + r"devInit.py")


info('')
info('************************************************************')
info('          Mandatory AFE initialization complete')
info('************************************************************')
info('')

script1.py

##########                     General settings:                     ##########

# VLBI Tx frequency plan details:
custom_clk 							= 0#2#										# Pick AFE scenario.
enableAnalogRepeater 				= True#False#								# Enable/disable AFE in analog loopback configuration (DACs transmitting from ADCs).
XbandEnable							= True#False#								# Enable/disable DAC sampling rate in X band.
dualLanePerSignal					= False#True#								# Pick 2 lanes (True) or 4 lanes (False) to transmit signal via JESD lines.
enableAdcDacSync					= True										# Enable sync signal between ADCs and DACs and FPGA by disabling LVDS sync that fixes GPIO pins.
separateLinks						= False
enableMux							= {'Tx': False, 'Rx': False}
useSpiSysref						= True#False#								# Enable (when debugging)/disable (in real operation) internal SYSREF signal.

ncoFreqModes 						= ["1KHz", "FCW"]
Fnco_tx1 							= 2245.0
Fnco_rx1							= 800.0
Fnco_tx4							= 9500#6812.5
Fnco_rx4							= 9500#637.5
syncLoopBack						= bool(1-enableAnalogRepeater)
jesdLoopbackEn 						= bool(enableAnalogRepeater)
enableLVDSsync						= bool(1-enableAdcDacSync)
fbJesdTxSyncMux						= 3 if enableLVDSsync else 1


if custom_clk == 0:
	# TI template configuration at different clock reference
	f0 								= 122.88
	Nrx								= 24
	Nddc							= 6
	Ntx 							= 4
	NFRef							= 4
	NfpgaRefClk						= 2
	NinputClk						= 12
	LMFSHdRx              			= ['44210', '44210', '44210', '44210']
	LMFSHdFb						= ['22210', '22210']
	LMFSHdTx						= ['44210', '44210', '44210', '44210']
	jesdSystemMode					= [3, 3]
elif (custom_clk == 1):
	# Desired configuration with proper data rates, sampling rates, and bandwidths
	f0 								= 163.68
	Nrx								= 18
	Nddc							= 6
	Ntx 							= 4
	NFRef							= 1
	NfpgaRefClk						= 1
	NinputClk						= 1
	LMFSHdRx              			= ['22210', '22210', '22210', '22210']
	LMFSHdFb						= ['22210', '22210']
	LMFSHdTx						= ['22210', '22210', '22210', '22210']
	jesdSystemMode					= [3, 3]
elif custom_clk == 2:
	# Symmetric JESD configuration
	f0 								= 163.68
	Nrx								= 12
	Nddc							= 6
	NFRef							= 1
	NfpgaRefClk						= 1
	NinputClk						= 1
	LMFSHdFb						= ['22210', '22210']
	Ntx 							= 5 if XbandEnable else 3
	Nlanes 							= '2' if dualLanePerSignal else '4'
	Nconv 							= Nlanes
	LMFSHdTx 						= [Nlanes+Nconv+'210']*4
	LMFSHdRx              			= LMFSHdTx
	jesdSystemMode					= [3, 3]
	
Nduc								= Nddc*Ntx
info('Tx & Rx LMFSHd settings: '+LMFSHdTx[0])


info('')
info('------------------------------------------------------------')
info('User configuration:')
if enableAnalogRepeater:
	info('     Analog repeater') 
else:
	info('     Digital repeater')
if XbandEnable:
	info('     DAC sampling in X band enabled') 
else:
	info('     DAC sampling in X band disabled')
if enableAdcDacSync:
	info('     LVDS sync disabled - ADC and DAC sync enabled') 
else:
	info('     LVDS sync enabled - ADC and DAC sync disabled')
if custom_clk:
	info('     External clock reference used: '+str(f0)+'MHz')
else:
	info('     Internal AFE clock reference used: '+str(f0)+'MHz')
info('------------------------------------------------------------')


info('')
info('************************************************************')
info('          User parametrization complete')
info('************************************************************')
info('')

script2.py

# AFE general settings
AFE.systemStatus.loadTrims			= 1
setupParams.skipFpga 				= 1
setupParams.fpgaRefClk 				= f0*NfpgaRefClk
sysParams							= AFE.systemParams
sysParams.FRef 						= f0*NFRef
sysParams.executeLinkUpSequenceSeparately = separateLinks

##########               Analog settings: AFE 79XX EVM               ##########

# General system settings	
sysParams.RRFMode   				= 0
sysParams.modeTdd					= 0
sysParams.adcSelect0				= [0, 1, 2]
sysParams.adcSelect1				= [0, 1, 2]
sysParams.useSpiSysref				= useSpiSysref
sysParams.sysrefTermination			= 0
sysParams.ncoFreqMode				= ncoFreqModes[custom_clk != 0]
sysParams.spiMode					= 1

# ADC settings
sysParams.FadcRx 					= f0*Nrx
info('ADC sampling rate: '+str(sysParams.FadcRx)+'MHz')
sysParams.rxEnable 					= [1, 1, 1, 1]
sysParams.externalClockRx 			= 0
sysParams.halfRateModeRx 			= [0, 0]
sysParams.ddcFactorRx 				= [Nddc, Nddc, Nddc, Nddc]
info('ADC down-conversion factors: '+str(sysParams.ddcFactorRx))
sysParams.numBandsRx 				= [0, 0, 0, 0]
sysParams.numRxNCO 					= 1
sysParams.ncoRxMode					= [0, 0]
sysParams.broadcastRxNcoSel			= 0
sysParams.rxNco0 					= [ [Fnco_rx1, Fnco_rx1], 
										[870.0, 870.0], 
										[637.5, 637.5], 
										[Fnco_rx4, Fnco_rx4]]
info('ADC NCOs: '+str(sysParams.rxNco0[0][0])+'MHz, '+str(sysParams.rxNco0[1][0])+'MHz, '+str(sysParams.rxNco0[2][0])+'MHz, '+str(sysParams.rxNco0[3][0])+'MHz')
sysParams.rxNco1 					= [ [Fnco_rx1, Fnco_rx1], 
										[870.0, 870.0], 
										[637.5, 637.5], 
										[Fnco_rx4, Fnco_rx4]]

# FB settings
sysParams.FadcFb					= sysParams.FadcRx
info('FB ADC sampling rate: '+str(sysParams.FadcFb)+'MHz')
sysParams.fbEnable 					= [0, 0]
sysParams.halfRateModeFb 			= [0, 0]
sysParams.ddcFactorFb 				= [Nddc, Nddc]
info('FB ADC down-conversion factors: '+str(sysParams.ddcFactorFb))
sysParams.numBandsFb				= [0, 0]
sysParams.numFbNCO 					= 1
sysParams.ncoFbMode					= 0
sysParams.fbNco0 					= [1000, 1000]
sysParams.fbNco1 					= [1000, 1000]
sysParams.fbNco2 					= [1000, 1000]
sysParams.fbNco3 					= [1000, 1000]
info('FB ADC NCOs: '+str(sysParams.fbNco0[0])+'MHz, '+str(sysParams.fbNco1[0])+'MHz')

# DAC settings
# DAC sampling rate must fall into one of the following frequency ranges (due to pll restrictions): [7.2 GHz, 7.68 GHz] or [8.8 GHz, 9.1 GHz] or [9.7 GHz, 10.24 GHz] or [11.6 GHz, 12.08 GHz]
sysParams.Fdac 						= sysParams.FadcRx*Ntx
info('DAC sampling rate: '+str(sysParams.Fdac)+'MHz')
sysParams.txEnable 					= [1, 1, 1, 1]
sysParams.externalClockTx			= 0
sysParams.halfRateModeTx 			= [0, 0]
sysParams.ducFactorTx 				= [Nduc, Nduc, Nduc, Nduc]
info('DAC up-conversion factors: '+str(sysParams.ducFactorTx))
sysParams.numBandsTx 				= [0, 0, 0, 0]
sysParams.numTxNCO 					= 1
sysParams.combineDucMode 			= [0, 0]
sysParams.enableDacInterleavedMode 	= 0
sysParams.ncoTxMode					= [0, 0]
sysParams.broadcastTxNcoSel			= 0
sysParams.txNco0	 				= [ [Fnco_tx1, Fnco_tx1],
										[5020.0, 5020.0], 
										[8212.5, 8212.5], 
										[Fnco_tx4, Fnco_tx4]]
sysParams.txNco1 					= [ [Fnco_tx1, Fnco_tx1],
										[5020.0, 5020.0], 
										[8212.5, 8212.5], 
										[Fnco_tx4, Fnco_tx4]]
info('DAC NCOs: '+str(sysParams.txNco0[0][0])+'MHz, '+str(sysParams.txNco0[1][0])+'MHz, '+str(sysParams.txNco0[2][0])+'MHz, '+str(sysParams.txNco0[3][0])+'MHz')


info('')
info('************************************************************')
info('          Analog front end setup complete')
info('************************************************************')
info('')

script3.py

##########               JESD204 settings AFE 79XX EVM               ##########

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.jesdSystemMode			= jesdSystemMode
sysParams.serdesFirmware			= 1
sysParams.jesdABLvdsSync			= enableLVDSsync
sysParams.jesdCDLvdsSync			= enableLVDSsync
sysParams.syncLoopBack				= syncLoopBack
sysParams.jesdLoopbackEn			= jesdLoopbackEn
	
	
sysParams.LMFSHdRx					= LMFSHdRx
sysParams.jesdRxProtocol			= [0, 0]
sysParams.jesdRxLaneMux				= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.jesdRxRbd					= [4, 4]
sysParams.rxJesdTxScr				= [1, 1, 1, 1]
sysParams.rxJesdTxK					= [16, 16, 16, 16]
sysParams.rxJesdTxSyncMux			= [0, 0, 0, 0]
sysParams.rxDataMux					= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.serdesRxLanePolarity		= [0, 0, 0, 0, 0, 0, 0, 0]
sysParams.adcDataMuxEn				= enableMux['Tx']
	
	
sysParams.LMFSHdFb					= LMFSHdFb
sysParams.fbJesdTxScr				= [1, 1]
sysParams.fbJesdTxK					= [16, 16]
sysParams.fbJesdTxSyncMux			= [fbJesdTxSyncMux, fbJesdTxSyncMux]
sysParams.fbDataMux					= [0, 1]
	
	
sysParams.LMFSHdTx					= LMFSHdTx
sysParams.jesdTxProtocol			= [0, 0]
sysParams.jesdTxLaneMux				= [0, 1, 2, 3, 4, 5, 6, 7]
#sysParams.jesdTxRbd					= [4, 4]
sysParams.jesdRxScr					= [1, 1, 1, 1]
sysParams.jesdRxK					= [16, 16, 16, 16]
sysParams.jesdRxSyncMux				= [0, 0, 0, 0]
sysParams.txDataMux					= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.serdesTxLanePolarity		= [0, 0, 0, 0, 0, 0, 0, 0]
sysParams.dacDataMuxEn				= enableMux['Rx']
#sysParams.serdesTxPreCursor			= [6, 6, 6, 6, 6, 6, 6, 6]
#sysParams.serdesTxPostCursor		= [0, 0, 0, 0, 0, 0, 0, 0]
#sysParams.serdesTxMainCursor		= [3, 0, 0, 0, 0, 0, 0, 3]
sysParams.setIlaParams				= 1
sysParams.jesdTxIlaM				= [8, 8, 2, 8, 8, 2]
sysParams.jesdTxIlaLid				= [0, 1, 2, 3, 4, 5, 6, 7]
sysParams.jesdTxIlaL				= [4, 4, 2, 4, 4, 2]


##########                         Dummy txt                         ##########

sysParams.gpioMapping={ 'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}


info('')
info('************************************************************')
info('          JESD setup complete')
info('************************************************************')
info('')

script4.py

##########              Clock distribution mode setting              ##########

setupParams.skipLmk					= 0
lmkParams.pllEn 					= (custom_clk == 0)
lmkParams.inputClk 					= f0*NinputClk
lmkParams.sysrefFreq				= lmkParams.inputClk#f0*Nrx/1024
lmkParams.lmkFrefClk				= 1
lmkParams.lmkPulseSysrefMode 		= 0
#AFE.systemStatus.sysrefFreq		= lmkParams.inputClk

lmk.rawWriteLogEn 					= 1
lmk.logEn 							= 1

logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x01
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1

device.optimizeWrites				= 0
device.rawWriteLogEn				= 1
device.delay_time                   = 0

setupParams.skipLmk				= False
AFE.initializeConfig()
lmkParams.sysrefFreq			= AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode 	= 0
AFE.LMK.lmkConfig()
# Force Latte to program the LMK outputs (relevant to the FPGA) in bypass/distribution mode
lmk.head.page.DCLK0_SDCLK1_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
lmk.head.page.DCLK8_SDCLK9_controls.Analog_Dig_Delay.sdclk_mux=1
lmk.head.page.DCLK12_SDCLK13_controls.Analog_Dig_Delay.dclk_mux_lt_1_0_gt_=2
setupParams.skipLmk				= True
	
	
info('')
info('************************************************************')
info('          LMK setup complete')
info('************************************************************')
info('')

'''
AFE7920EVM has enabled wire-probes on the following LMK outputs:
- DCLKOUT0  (C275): thick, yellow
- SDCLKOUT1 (R353): thick, light green
- DCLKOUT2  (R345): thin, 
- SDCLKOUT3 (R352): thin, 
- SDCLKOUT9 (C259): thick, red
'''

script5.py

AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15)


info('')
info('************************************************************')
info('          AFE bringup complete')
info('************************************************************')
info('')

此致、

Željko μ A

0 admin 2 年多前

TI__Guru**** 2470720 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好！ Željko

我们将在实验练习中运行这些脚本并验证其功能。您能否检查是否连接到其他 Rx 和 Tx 对、看看您是否获得预期输出？例如、如果输入连接到 RxA、您是否能够从 TxA 获得预期输出？请注意、应根据这些通道的 NCO 调整输入频率。

此致、

Vijay

0 admin 2 年多前

TI__Guru**** 2470720 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Zeljko：

我已经在我们的设置中测试了您的脚本、由于 LMK 输出不同、对时钟设置做了一些小改动、然后我能够在 TXD 上得到输出。在此设置中、我对 RxD 的输入设置为9.52GHz、0dBm、我看到 TxD 上的输出为9.52GHz。请在设置上尝试相同的输入。

在进行设置时需要注意的一点是、对于您的"custom_clk=0"配置、AFE 的 LMK 时钟输出不应处于旁路模式、因为此模式使用 LMK PLL。在使用 LMK PLL 的情况下、AFE 的 LMK 输出应设置为分频器模式、分频器值为6、以提供491.52MHz 参考时钟。

此致、

David Chaparro

射频与微波（参考译文帖）

射频与微波（参考译文帖）(Read Only)

[参考译文] AFE7950EVM：DAC 输出端为低功耗