[参考译文] AFE7950-SP：无 I 通道输出

尊敬的 Byungsoo：

如果您使用频谱分析仪查看 DAC 输出、您是否会看到两个 Tx 通道上存在问题？ 当您说没有 I channel 输出时、它始终为"0"或噪声？  

我注意到 Rx 端的一个问题是您已将 NCO 设置在奈奎斯特边界上、这不应该执行。 这样做时、您将看到奈奎斯特边界和音调的图像。 使用抽取因子"2"时、您应该将 NCO 置于奈奎斯特区域的中心。

您能否检查您看到的问题是否是由于 NCO 位于奈奎斯特边界上引起的？  

我针对您的模式测试了以下脚本。

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 491.52M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 500
sysParams.FadcRx		= 3000
sysParams.FadcFb		= 3000
sysParams.Fdac			= 3000*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
sysParams.RRFMode = 5

##############		Digital Chain		##############

		#####	RX	#####
sysParams.rxEnable		=	[1,1,0,0]
sysParams.ddcFactorRx	=	[2,2,2,2]				#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[3750,3750],			#Band0, Band1 for RXA 
							[3750,3750],        	#Band0, Band1 for RXB 
							[3750,3750],        	#Band0, Band1 for RXC 
							[3750,3750]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.fbEnable		=	[False,False]
sysParams.ddcFactorFb	=	[6,6]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[4500,4500]				#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.txEnable		=	[1,1,0,0]
sysParams.ducFactorTx	=	[8,8,8,8]			#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[4500,4500],			#Band0, Band1 for TXA 
							[4500,4500],        	#Band0, Band1 for TXB 
							[4500,4500],        	#Band0, Band1 for TXC 
							[4500,4500]]        	#Band0, Band1 for TXD


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [2,2]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["44210","44210","44210","44210"]
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [False]*4
sysParams.fbJesdTxScr	= [False]*2

sysParams.rxJesdTxK		= [1,1,1,1]
sysParams.fbJesdTxK		= [1,1]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [2,2]
sysParams.LMFSHdTx		= ["44210","44210","44210","44210"]
sysParams.txDataMux		= [6,7,2,3,4,5,0,1]
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [False]*4
sysParams.jesdRxK		= [1,1,1,1]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= True	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= False
lmkParams.inputClk		= 1500 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 250 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)	# bit-wise; 4R,2F,4T

此致、

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尊敬的 Byungsoo：

无法测试提供的脚本、因为 TSW14J57不支持64b66b 编码。  

如果您希望在自己的设置上进行测试、则只需调整 sysParams.txNco0和 sysParams.rxNco0 参数中的 NCO 频率。  

此致、

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