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器件型号：AFE7950EVM Thread 中讨论的其他器件： AFE7950
工具与软件：
早上好。
我们的团队正在尝试使用 Latte 软件配置连接到 TSW14J58的 AFE7950EVM 板。 我们希望对 ADC 进行配置、使一个块的 ADC 抽取值为3、另一个块的 ADC 抽取值为2、如数据表中所示的选项。 
选择的系统模式为 rrfmode 0、其中 Rx、Tx 和 FB 处于 FDD 模式 
但是、一旦 Latte 编译了配置、就 会返回错误消息"Current RX DDC Factor setting 在 FDD 模式下不受支持"。 查看 Latte 的 python 代码、可在软件上将该限制硬编码、其中表示当输出速率为1000和1500、ADC 采样率为3,000,2500或2000时、FFD 模式不可用。
这是为什么？ 是否有办法在其他配置中实现类似行为？
预期行为如下：4Rx 和4Tx 无反馈、64b/66b、3600MHz 单频带、两个 ADC 输出速率为1000Msps、两个 ADC 输出速率为1500Msps、2个 DAC 输入速率为1000Msps、其他2个 DAC 输入速率为1500Msps。 为了避免 DAC 出现错误、我们设计中的有效 DAC 采样率将为6000和12000MSPS。
Latte 中使用的当前启动文件如下所示：
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_24410; Data Rate = 245.76M ---> To capture 4 RX channels
#In HSDC Pro ADC tab, Select AFE79xx_1x2FB_44210; Data Rate = 491.52M ---> To capture 2 FB channels
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = 0 # setup FPGA (TSW14J58)
############## Top Level ##############
sysParams.FRef = 491.52 # Recommended 2949.12/6 (interno o externo, ahora es interno)
sysParams.FadcRx = 2949.12 # Dependen de si el reloj es interno o externo (ahora mismo es interno )
sysParams.FadcFb = 2949.12 # Dependen de si el reloj es interno o externo (ahora mismo es interno )
sysParams.Fdac = 2949.12*2 # Dependen de si el reloj es interno o externo (ahora mismo es interno )
sysParams.externalClockRx=False # Dependen de si el reloj es interno o externo (ahora mismo es interno )
sysParams.externalClockTx=False # Dependen de si el reloj es interno o externo (ahora mismo es interno)
############## Digital Chain ##############
sysParams.RRFMode = 0 # FDD Mode. This is a typical FDD mode with 4TX, 4RX chains and 2 FB chains,
# where all RX and FB chains have independent ADCs
sysParams.ncoFreqMode = "FCW"
# Its possible to configur number of NCO by band
##### RX #####
sysParams.ddcFactorRx = [3,3,2,2] #DDC decimation factor for RX A, B, C and D
sysParams.numBandsRx = [0,0,0,0] # Single band
# Rx A B BW 500MHz -> Relacion 1000/3000 Msps - 3
# Rx B C BW 1GHz -> Relacion 1500/3000 Msps - 2
sysParams.rxNco0 = [[3600,3600], #Band0, Band1 for RXA (media entre 3.3-3.9 GHz)
[3600,3600], #Band0, Band1 for RXB (media entre 3.3-3.9 GHz)
[3600,3600], #Band0, Band1 for RXC
[3600,3600]] #Band0, Band1 for RXD
##### FB #####
sysParams.fbEnable = [False,False]
sysParams.ddcFactorFb = [3,3] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [3600,3600] #Band0 for FB1 and FB2
##### TX #####
sysParams.ducFactorTx = [6,6,4,4] #DUC interpolation factor for TX A, B, C and D
sysParams.numBandsTx = [0,0,0,0] # Single band
sysParams.txNco0 = [[4450,3600], #Band0, Band1 for TXA
[4450,3600], #Band0, Band1 for TXB
[4450,3600], #Band0, Band1 for TXC
[4450,3600]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [3,3] # case where, FB is not needed and only both channels of the RX
# are to be treated as a single JESD mapper
sysParams.jesdTxProtocol= [2,2] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["44210","44210","44210","44210"]
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.rxJesdTxScr = [False,False,False,False]
sysParams.fbJesdTxScr = [False,False]
sysParams.rxJesdTxK = [1,1,1,1] # Multiblock para 64b - 1
sysParams.fbJesdTxK = [1,1] # Multiblock para 64b - 1
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2T,
# this should be [[1,0,2,3],[5,4,6,7]]
##### DAC-JESD #####
sysParams.jesdRxProtocol= [2,2]
sysParams.LMFSHdTx = ["44210","44210","44210","44210"]
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2R
# this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd = [4, 4]
sysParams.jesdRxScr = [False,False,False,False]
sysParams.jesdRxK = [1,1,1,1] # Multiblock para 64b - 1
##### JESD Common #####
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack = False #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
############## LMK Params ##############
lmkParams.pllEn = True
lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 245.76 # 2949.12/12
############## Logging ##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x1 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()
AFE.TOP.overrideTdd(15,0,15) # bit-wise; 4R,0F,4T
希望有任何帮助。
感谢你能抽出时间。
Jose
