TMS320F28335: PWM输出正弦波形是反相的

ahs

Part Number: TMS320F28335

驱动板PWM低电平有效

设置了增减计数，计数值增加到调制信号时PWM输出高电平，计数值减小到调制信号时输出低电平；

调制信号设置：

Uga= 11.1*sinf(2*3.14159*50*tch*0.0001);
Ugb= 11.1*sinf(2*3.14159*50*tch*0.0001-0.6667*3.14159)+20;
Ugc= 11.1*sinf(2*3.14159*50*tch*0.0001+0.6667*3.14159);
tch+=1;
if (tch>200)
tch=1;

EA=Uga/Udc*2;
EB=Ugb/Udc*2;
EC=Ugc/Udc*2;
EPwm1Regs.CMPA.half.CMPA=EPWM_TBPRD*(EA+1)/2;
EPwm2Regs.CMPA.half.CMPA=EPWM_TBPRD*(EB+1)/2;
EPwm3Regs.CMPA.half.CMPA=EPWM_TBPRD*(EC+1)/2;

PWM具体设置如下：

EPwm1Regs.TBPRD = EPWM_TBPRD;
EPwm1Regs.TBCTR = 0x0000;
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.CMPA.half.CMPA = 0;

// EPwm1Regs.TBCTL.bit.FREE_SOFT = 0x2;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; //TBCLK=SYSCLK/(CLKDIV*HSPCLKDIV)
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.TBCTL.bit.PRDLD = 1;
EPwm1Regs.TBCTL.bit.CTRMODE = 0x2; //=2,up-down count mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = TB_SHADOW; //0,shadow mode
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; //active high mode,
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;

EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; //EPWM1A IN
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; //AHC mode,b invert
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //full enable

EPwm1Regs.DBRED = dead_band;
EPwm1Regs.DBFED = dead_band;

EPwm2Regs.TBPRD = EPWM_TBPRD;
EPwm2Regs.TBCTR = 0x0000;
EPwm2Regs.TBPHS.half.TBPHS = 0;
EPwm2Regs.CMPA.half.CMPA = 0;

// EPwm2Regs.TBCTL.bit.FREE_SOFT = 0x2;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; //TBCLK=SYSCLK/(CLKDIV*HSPCLKDIV)
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.PRDLD = 1;
EPwm2Regs.TBCTL.bit.CTRMODE = 0x2; //=2,up-down count mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;

EPwm2Regs.CMPCTL.bit.SHDWAMODE = TB_SHADOW; //0,shadow mode
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; //
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;

EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; //EPWM1A IN
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; //AHC mode,b invert
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //full enable

EPwm2Regs.DBRED = dead_band;
EPwm2Regs.DBFED = dead_band;

EPwm3Regs.TBPRD = EPWM_TBPRD;
EPwm3Regs.TBCTR = 0x0000;
EPwm3Regs.TBPHS.half.TBPHS = 0;
EPwm3Regs.CMPA.half.CMPA = 0;

// EPwm3Regs.TBCTL.bit.FREE_SOFT = 0x2;
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; //TBCLK=SYSCLK/(CLKDIV*HSPCLKDIV)
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTL.bit.PRDLD = 1;
EPwm3Regs.TBCTL.bit.CTRMODE = 0x2; //=2,up-down count mode
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;

EPwm3Regs.CMPCTL.bit.SHDWAMODE = TB_SHADOW; //0,shadow mode
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;

EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; //EPWM1A IN
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; //AHC mode,b invert
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //full enable

EPwm3Regs.DBRED = dead_band;
EPwm3Regs.DBFED = dead_band;

EALLOW;
EPwm1Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_HI;
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_HI;

EPwm2Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_HI;
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_HI;

EPwm3Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_HI;
EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_HI;
EDIS;

EPwm1Regs.ETSEL.bit.INTEN = 1;
EPwm1Regs.ETSEL.bit.INTSEL= ET_CTR_PRD;
EPwm1Regs.ETPS.bit.INTCNT = ET_1ST;
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;

EPwm1Regs.ETSEL.bit.SOCAEN=1;// enable soc TO START ADC
EPwm1Regs.ETSEL.bit.SOCASEL=ET_CTR_PRD;//soc at prd
EPwm1Regs.ETPS.bit.SOCAPRD= 1;