我的CPU1代码如下
#include "device.h" #include "F28x_Project.h" #include "board.h" #include <driverlib.h> // // Defines // #define IPC_CMD_READ_MEM 0x1001 #define IPC_CMD_RESP 0x2001 #define TEST_PASS 0x5555 #define TEST_FAIL 0xAAAA #define Num 10 #pragma DATA_SECTION(readData, "readData") uint16_t readData[Num]; uint16_t pass; //IPC通信变量 IPC_MessageQueue_t messageQueue; IPC_Message_t TxMsg, RxMsg; /** * main.c */ void main(void) { uint32_t i =0 ; Device_init(); // Initialize device clock and peripherals Interrupt_initModule(); // Initialize PIE and clear PIE registers. Disables CPU interrupts. IER = 0x0000; //CPU级中断使能 IFR = 0x0000; //清除CPU级中断标志 Interrupt_initVectorTable(); // Initialize the PIE vector table with pointers to ISR MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS13|MEMCFG_SECT_GS14, MEMCFG_GSRAMMASTER_CPU2); Board_init(); #ifdef _STANDALONE #ifdef _FLASH // // Send boot command to allow the CPU2 application to begin execution // Device_bootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH); #else // // Send boot command to allow the CPU2 application to begin execution // Device_bootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_RAM); #endif // _FLASH #endif // _STANDALONE Device_initGPIO(); // Initialize GPIO and configure the GPIO pin as a push-pull output // // Clear any IPC flags if set already // IPC_clearFlagLtoR(IPC_CPU1_L_CPU2_R, IPC_FLAG_ALL); // // Initialize message queue // IPC_initMessageQueue(IPC_CPU1_L_CPU2_R, &messageQueue, IPC_INT1, IPC_INT1); // // Synchronize both the cores // IPC_sync(IPC_CPU1_L_CPU2_R, SYNC_FLAG); EINT; // Enable Global Interrupt (INTM) ERTM; // Enable real-time interrupt (DBGM) for(i=0; i<Num; i++) { readData[i] = i; } TxMsg.command = IPC_CMD_READ_MEM; TxMsg.address = (uint32_t)readData;//强转为uint32_t TxMsg.dataw1 = Num; // Using dataw1 as data length TxMsg.dataw2 = 1; // Message identifier for (;;) { GPIO_togglePin(myGPIO99); DELAY_US(1000000); //IPC_sendMessageToQueue发送另一个核必须进行读取,否则会出现问题,并且采用非阻塞式发送也会出现问题 //如果是共同的RAM例如GSRAM则不需要校正 否则地址会有偏移 //MSGRAM则需要校正 IPC_sendMessageToQueue(IPC_CPU1_L_CPU2_R, &messageQueue, IPC_ADDR_CORRECTION_DISABLE, &TxMsg, IPC_BLOCKING_CALL); // IPC_sendCommand(IPC_CPU1_L_CPU2_R,IPC_FLAG1,IPC_ADDR_CORRECTION_DISABLE,0,0,0); } }
#include "device.h" #include "F28x_Project.h" #include "board.h" #include <driverlib.h> #define IPC_CMD_READ_MEM 0x1001 #define IPC_CMD_RESP 0x2001 #define TEST_PASS 0x5555 #define TEST_FAIL 0xAAAA #define Num 10 uint16_t readData_CPU2[Num]; uint16_t sendData_CPU2[Num]; #pragma DATA_SECTION(readData_CPU2, "readData_CPU2") #pragma DATA_SECTION(sendData_CPU2, "sendData_CPU2") uint16_t IPC_Flag = 0; uint16_t IPC_Count2 = 0; bool status = false; #define myGPIO133 133 IPC_MessageQueue_t messageQueue; IPC_Message_t TxMsg, RxMsg; __interrupt void IPC_1_ISR(void); /** * main.c */ void main(void) { Device_init(); // Initialize device clock and peripherals Device_initGPIO(); // Initialize GPIO and configure the GPIO pin as a push-pull output Interrupt_initModule(); // Initialize PIE and clear PIE registers. Disables CPU interrupts. IER = 0x0000; //CPU级中断使能 IFR = 0x0000; //清除CPU级中断标志 Interrupt_initVectorTable(); // Initialize the PIE vector table with pointers to ISR Board_init(); // // Clear any IPC flags if set already // IPC_clearFlagLtoR(IPC_CPU2_L_CPU1_R, IPC_FLAG_ALL); // // Initialize message queue // IPC_initMessageQueue(IPC_CPU2_L_CPU1_R, &messageQueue, IPC_INT1, IPC_INT1); // // Synchronize both the cores. // IPC_sync(IPC_CPU2_L_CPU1_R, SYNC_FLAG); EINT; // Enable Global Interrupt (INTM) ERTM; // Enable real-time interrupt (DBGM) for (;;) { ; } } __interrupt void IPC_1_ISR(void) { uint32_t i; GPIO_togglePin(myGPIO133); DELAY_US(1000000); // // Read the message from the message queue // IPC_readMessageFromQueue(IPC_CPU2_L_CPU1_R, &messageQueue, IPC_ADDR_CORRECTION_DISABLE, &RxMsg, IPC_NONBLOCKING_CALL); if(RxMsg.command == IPC_CMD_READ_MEM) { status = true; IPC_Count2++; // // Read and compare data // for(i=0; i<RxMsg.dataw1; i++) { if(*((uint16_t *)RxMsg.address + i) != i)//强转为数组类型 status = false; readData_CPU2[i]=*((uint16_t *)RxMsg.address + i); sendData_CPU2[i]=readData_CPU2[i]+1; } } // IPC_readCommand(IPC_CPU2_L_CPU1_R,IPC_FLAG1,IPC_ADDR_CORRECTION_DISABLE,0,0,0); // // Acknowledge the flag // IPC_ackFlagRtoL(IPC_CPU2_L_CPU1_R, IPC_FLAG1); // // Acknowledge the PIE interrupt. // Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1); }