To synchronize the EPWM counter with the CLB, I am using the CLB to generate a synchronization pulse that is routed via the EPWMXBAR to the EPWM Digital Compare (DC) module. I have some questions now.
1.I noticed that there is a pulse generation section in the DC event triggering part, and I’m not entirely sure how long the pulse width will be.
I routed the DCxEVT1.sync signal to the OUTPUTXBAR and found that the synchronization pulse width is much wider than 1 TBCLK (both SYSCLK and TBCLK are 120 MHz). Is this due to pulse-stretched behavior on EXTSYNCOUT? Will the actual pulse width of DCxEVT.sync be different from the width output to the GPIO?
2.According to the reference manual, EPWMxSYNCI is activated by rising edge. But what about the signal from the DCxEVT1.sync?
Would a sustained high-level signal cause continuous synchronization?
