Part Number: TMS320F28377D
Other Parts Discussed in Thread: TLV62568
Power Architecture:
12V → LV2842XLVDDCR → 5V ─┬→ TLV62568DBVR → 3.3V (VDDIO)
└→ TLV62568DBVR → 1.2V (VDD)- DSP: TMS320F28377PTP
- VREGENZ: tied to VDDIO (internal VREG disabled)
Power Sequencing (Scope Measurements):
| Trace | Rail | Soft-Start Time | Notes |
|---|---|---|---|
| Fig.1 | 12V Input | 10 ms | External PSU soft-start |
| Fig.2 | 12V→5V (LV2842) | 2.5 ms | Normal |
| Fig.3 (Yellow) | 5V→3.3V (TLV62568) | <1 ms | Normal |
| Fig.3 (Green) | 5V→1.2V (TLV62568) | <1 ms | Clamped to 2.1V |
- Both 3.3V and 1.2V are generated by identical TLV62568DBVR converters; ramp times are both <1 ms, nearly simultaneous
- Total system power: 11.6V input / 0.105A / 1.22W — no abnormal power draw
- DSP becomes slightly warm after power-up; no obvious overheating
Failure Scale:
7 TMS320F28377PTP devices have been damaged to date, all with identical failure symptoms. 100% failure rate on first power-up.
Timeline of Investigation:
- Original design included a PMOS inrush limiter (499kΩ×2 divider + 1μF cap, ≈16.6ms) ahead of the 24V input, with the external PSU itself providing a 25ms soft-start. First DSP was found with VDD clamped to ~2.1V
- Changed inrush capacitor from 1μF to 100nF (≈1.6ms), no improvement. PMOS inrush waveform showed oscillation dips. Eventually removed the PMOS inrush circuit entirely (shorted)
- After removal, 3.3V and 1.2V ramp times both reduced to <1ms. However, subsequent DSPs continued to fail identically — VDD clamped to 2.1V, stabilizing at 2.0V
- Removed the 1.2V TLV62568 (U5), applied only 3.3V to the board — VDD rail still measured ~2.0V, confirming the voltage originates from within the DSP (ESD diodes conducting from VDDIO to VDD)
- Added a 20Ω dummy load from VDD to GND (2.0V ÷ 20Ω ≈ 100mA). VDD voltage was NOT pulled down — indicating back-feed current far exceeds 100mA, consistent with a low-impedance path having formed internally
- Every DSP failed on first power-up after soldering, not gradually over accumulated runtime. 7 devices, 100% failure rate, identical symptoms
What Has Been Ruled Out:
| Item | Status |
|---|---|
| 1.2V DC-DC feedback network: Rtop=100kΩ / Rbottom=100kΩ, Vref=0.6V → Vout=1.2V (verified without DSP) | ✓ |
| VREGENZ correctly tied to VDDIO | ✓ |
| Power sequencing optimized to <1ms synchronous ramps | ✓ |
| TLV62568 tested standalone — outputs 1.2V without DSP soldered | ✓ |
| Soldering: reflow profile within spec, no shorts or cold joints | ✓ |
| Partial schematic shown in Fig.4 |
Questions:
-
Seven F28377 devices failed 100% on first power-up with identical symptoms (VDDIO→VDD low-impedance path, VDD clamped to ~2.0V). The TLV62568 does not support pre-bias startup — when VDD is pre-biased to 2.0V by the DSP's ESD diodes, the converter detects Vout > Vref and refuses to start switching. Could this sustained reverse-bias condition on the ESD diodes cause them to degrade into a low-impedance short?
-
The datasheet requires VDDIO and VDD track within 0.3V of each other, but provides no guidance on sub-ms startup delay mismatch when using independent discrete converters of the same model. Both TLV62568 converters ramp in <1ms nearly simultaneously — is there a known issue where even microsecond-level startup skew causes *** ESD structure degradation?
-
For this power architecture (two independent TLV62568 converters for VDDIO and VDD), would TI recommend using the VDD converter's Power Good output to enable the VDDIO converter, thereby guaranteeing VDD is established before VDDIO? Or is there another recommended sequencing scheme to prevent this failure mode?
Figure.1
Figure.2
Figure.3
