如何给C2000的CPU定时器分频

请注意，PSC和PSCH本来就是只读位，设置分频应该从TDDR和TDDRH位来设置

CPU-Timer Prescale Counter. These bits hold the current prescale count for the timer. For every timer clock
source cycle that the PSCH:PSC value is greater than 0, the PSCH:PSC decrements by one. One timer clock
(output of the timer prescaler) cycle after the PSCH:PSC reaches 0, the PSCH:PSC is loaded with the contents
of the TDDRH:TDDR, and the timer counter register (TIMH:TIM) decrements by one. The PSCH:PSC is also
reloaded whenever the timer reload bit (TRB) is set by software. The PSCH:PSC can be checked by reading
the register, but it cannot be set directly. It must get its value from the timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.

PSC的解释，这只是一个active寄存器的分频值，每次减到0后，让timer clock输出一次，然后把TDDR/TDDRH的值load到PSC/PSCH一次。这是他的工作原理，所以TDDR/TDDRH可以视为shadow寄存器，每次更新后，要等到当次PSC/PSCH减到0才会从新load。下面是TDDR/TDDRH的解释：

CPU-Timer Prescale Counter. These bits hold the current prescale count for the timer. For every timer clock
source cycle that the PSCH:PSC value is greater than 0, the PSCH:PSC decrements by one. One timer clock
(output of the timer prescaler) cycle after the PSCH:PSC reaches 0, the PSCH:PSC is loaded with the contents
of the TDDRH:TDDR, and the timer counter register (TIMH:TIM) decrements by one. The PSCH:PSC is also
reloaded whenever the timer reload bit (TRB) is set by software. The PSCH:PSC can be checked by reading
the register, but it cannot be set directly. It must get its value from the timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.