This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
我使用了DSP自己的PWM端口进行输出,,捕获后值是对的,但接入其他方波信号,出现捕获的ECAP1~ECAP4值一样,用示波器观察,信号质量还可以,怎么回事
ECAP1 上升触发,ECAP2 下降触发,ECAP3 上升触发,,ECAP4 下降触发\在event4设置中断,读取数据. ECap2Regs.ECEINT.all = 0x0000; // Disable all capture interrupts
ECap2Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags
ECap2Regs.ECCTL1.bit.CAPLDEN = 0; // Disable CAP1-CAP4 register loads
ECap2Regs.ECCTL2.bit.TSCTRSTOP = 0; // Make sure the counter is stopped
// EC_ABS_MODE;
// Configure peripheral registers
ECap2Regs.ECCTL2.bit.CONT_ONESHT = 0; // continue
ECap2Regs.ECCTL2.bit.STOP_WRAP = 3; // Wrap after Capture Event 4 .
ECap2Regs.ECCTL1.bit.CAP1POL = EC_RISING; // Rising edge
ECap2Regs.ECCTL1.bit.CAP2POL = EC_FALLING; // Falling edge
ECap2Regs.ECCTL1.bit.CAP3POL = EC_RISING; // Rising edge
ECap2Regs.ECCTL1.bit.CAP4POL = EC_FALLING; // Falling edge
ECap2Regs.ECCTL1.bit.CTRRST1 = EC_ABS_MODE; // absolute time stamp
ECap2Regs.ECCTL1.bit.CTRRST2 = EC_ABS_MODE; // Difference operation
ECap2Regs.ECCTL1.bit.CTRRST3 = EC_ABS_MODE; // Difference operation
ECap2Regs.ECCTL1.bit.CTRRST4 = EC_DELTA_MODE; // Difference operation
ECap2Regs.ECCTL2.bit.SYNCI_EN = 0; // Enable sync in
ECap2Regs.ECCTL2.bit.SYNCO_SEL = 1; // disable sync signal out
ECap2Regs.ECCTL1.bit.CAPLDEN = 1; // Enable capture units
ECap1Regs.ECCTL2.bit.CAP_APWM = EC_CAP_MODE;
// ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; // Start Counter
// ECap1Regs.ECCTL2.bit.REARM = 1; // Rearm one-Shot
// ECap1Regs.ECCTL1.bit.CAPLDEN = 1; // Enable CAP1-CAP4 register loads
ECap2Regs.ECEINT.bit.CEVT4 = 1; // 2 events = interrupt
你好。根据你设置,只有CAP4是Delta模式,也就是说Counter在CEVT4后会复位,其他三个事件后是不复位的。
假设,输入的PWM周期为T,且不发生变化,占空比为D,那么,4个CAP寄存器的值应为:
CAP1=(1-D)*T*SYSCLK // 低电平时间
CAP2=T*SYSCLK
CAP3=(2-D)*T*SYSCLK
CAP4=2*T*SYSCLK
由于每次CEVT4后,Counter都会复位,所以四个CAP寄存器的数值总是不变的。
请问你的测试结果是否如此?