How to make SCI always send and receive?

I want to keep watching rdata's changes. Hope to it can always receive rdata.

This is my code:

#include "DSP28x_Project.h"
#include <stdio.h>
void scia_echoback_init(void);
void scia_fifo_init(void);
void scia_xmit(void);
int i,B;

char sdata[8]={0x01, 0x03, 0x00, 0x00, 0x00, 0x01, 0x84, 0x0A};
char rdata[7];

int main(void)
{
InitSysCtrl();
InitSciaGpio();
InitEPwm1Gpio();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

EALLOW;
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1;
EDIS;

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

for(i=0; i< 100; i++)
{ DELAY_US(10000L);
scia_fifo_init(); // Initialize the SCI FIFO
scia_echoback_init(); // Initialize SCI for echoback
scia_xmit();
DELAY_US(10000L);
while(SciaRegs.SCIFFRX.bit.RXFFST !=1) { } // wait for XRDY =1 for empty state
DELAY_US(10000L);
for(i=0; i< 7; i++)
{
rdata[i] = SciaRegs.SCIRXBUF.all;
}
i=0;
}

}
void scia_echoback_init()
{
SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.all =0x0003;
SciaRegs.SCICTL2.bit.TXINTENA =0;
SciaRegs.SCICTL2.bit.RXBKINTENA =0;
SciaRegs.SCIHBAUD =0x0001; // 9600 baud @LSPCLK = 37.5MHz.
SciaRegs.SCILBAUD =0x00E7;
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
}
// Transmit a character from the SCI
void scia_xmit()
{
while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}
for(i=0; i< 8; i++)
{
SciaRegs.SCITXBUF=sdata[i];
}
}
// Initialize the SCI FIFO
void scia_fifo_init()
{
SciaRegs.SCIFFTX.all=0xE040;
SciaRegs.SCIFFRX.all=0x204f;
SciaRegs.SCIFFCT.all=0x0;
}