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2838x下载程序问题

user6251321
Intellectual 395 points


编译程序可以通过，但是：

1、下载程序时总是报 C28xx_CPU1: Loader: One or more sections of your program falls into a memory region that is not writable.  These regions will not actually be written to the target.  Check your linker configuration and/or memory map.

2、并且通过Expression读取寄存器值时，总是显示 Memory map prevented reading 0x5F825@Program;

3、运行程序时，总是跳入非法中断，请问是为什么。

  • 0
    TI__Guru**** 252096 points
    请问您是使用的TI例程吗？根据错误提示像是cmd文件的问题
  • 0 回复 Susan Yang
    Intellectual 395 points
    是的，我将TI例程中的CMD文件进行了修改，但是我并没有发现修改后的CMD文件有什么问题，您这边能帮忙看一下吗
  • 0
    TI__Guru** 101655 points
    问题1可能是target configuration配置问题，确保target configuration中的目标板和仿真器型号都是正确匹配的
    问题2参考一下：e2echina.ti.com/.../293979
    问题3具体是哪个非法中断？尝试一下单步运行并且看一下是执行到哪个语句的时候会跳到非法中断
  • 0 回复 Green Deng
    Intellectual 395 points
    配置检查了没发现问题；编译器版本工程中的选项只有一个TI v18.12.2.LTS；单步F5运行不进非法中断，单步F6运行和全速运行直接就进非法中断了
  • 0 回复 Susan Yang
    Intellectual 395 points
    您好，请问您收到给您发的.cmd 吗？那个配置有问题吗，谢谢。
  • 0 回复 user6251321
    TI__Guru**** 252096 points
    收到了您的cmd文件

    由于手边没有这个板子，所以没有办法上手测试。代码本身没有问题的话，可能是rogue 指针或堆不足导致的，建议您增大一下堆栈heap 和 stack的大小试试
  • 0 回复 Susan Yang
    Intellectual 395 points
    好的，谢谢，麻烦您你那边试了后，告知一下。谢谢。
  • 0 回复 user6251321
    TI__Guru**** 252096 points
    很抱歉，由于我手边没有这个板子，所以没有办法上手测试。请您增大一下堆栈heap 和 stack的大小试试
  • 0 回复 Susan Yang
    Intellectual 395 points
    好的。我刚才增大了，还是不行，就是这个问题还是一直出现：C28xx_CPU1: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.
  • 0 回复 user6251321
    TI__Guru**** 252096 points

    请您试一下下面的cmd文件

    在此使用的是   RAMGS101112      : origin = 0x017000, length = 0x003000

    MEMORY
{
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
   BEGIN            : origin = 0x000000, length = 0x000002
   BOOT_RSVD        : origin = 0x000002, length = 0x0001AF     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x0001B1, length = 0x00024F
   RAMM1            : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD       : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD01           : origin = 0x00C000, length = 0x001000
   RAMLS02          : origin = 0x008000, length = 0x001800
   RAMLS3           : origin = 0x009800, length = 0x000800
   RAMLS4           : origin = 0x00A000, length = 0x000800
   RAMLS56          : origin = 0x00A800, length = 0x001000
   RAMLS7           : origin = 0x00B800, length = 0x000800
   RAMGS0           : origin = 0x00D000, length = 0x001000
   RAMGS1           : origin = 0x00E000, length = 0x001000
   RAMGS2           : origin = 0x00F000, length = 0x001000
   RAMGS3           : origin = 0x010000, length = 0x001000
   RAMGS4           : origin = 0x011000, length = 0x001000
   RAMGS5           : origin = 0x012000, length = 0x001000
   RAMGS6           : origin = 0x013000, length = 0x001000
   RAMGS7           : origin = 0x014000, length = 0x001000
   RAMGS8           : origin = 0x015000, length = 0x001000
   RAMGS9           : origin = 0x016000, length = 0x001000
   RAMGS101112      : origin = 0x017000, length = 0x003000
   RAMGS13          : origin = 0x01A000, length = 0x001000
   RAMGS14          : origin = 0x01B000, length = 0x001000
   RAMGS15          : origin = 0x01C000, length = 0x000FF8
//   RAMGS15_RSVD     : origin = 0x01CFF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   /* Flash sectors */
   FLASH0           : origin = 0x080000, length = 0x002000	/* on-chip Flash */
   FLASH1           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASH2           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASH3           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASH4           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASH5           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASH6           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASH7           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASH8           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASH9           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASH10          : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASH11          : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASH12          : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASH13          : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
   CPU1TOCPU2RAM    : origin = 0x03A000, length = 0x000800
   CPU2TOCPU1RAM    : origin = 0x03B000, length = 0x000800

   CPUTOCMRAM       : origin = 0x039000, length = 0x000800
   CMTOCPURAM       : origin = 0x038000, length = 0x000800

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
   RESET           	: origin = 0x3FFFC0, length = 0x000002
}


SECTIONS
{
   codestart        : > BEGIN
   .text            : >> RAMD01 | RAMLS02 | RAMLS3 | RAMGS101112
   .cinit           : > RAMM0
   .switch          : > RAMM0
   .reset           : > RESET, TYPE = DSECT /* not used, */

   .stack           : > RAMM1
#if defined(__TI_EABI__)
   .bss             : >> RAMLS56 | RAMGS101112
   .bss:output      : > RAMLS3
   .init_array	    : > RAMM0
   .const           : > RAMLS56
   .data			: >> RAMGS101112 //RAMLS56 |
   .sysmem			: > RAMLS4
#else
   .pinit           : > RAMM0
   .ebss            : >> RAMLS56
   .econst          : > RAMLS56
   .esysmem         : > RAMLS56
#endif

   ramgs0 : > RAMGS0, type=NOINIT
   ramgs1 : > RAMGS1, type=NOINIT

   MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
   MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
   MSGRAM_CPU_TO_CM   > CPUTOCMRAM, type=NOINIT
   MSGRAM_CM_TO_CPU   > CMTOCPURAM, type=NOINIT

    .TI.ramfunc : {} > RAMM0

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/


    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                 	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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